PCA2125TS datasheet(7/40 Pages) NXP

7 / 40 page

PCA2125_00

Preliminary data sheet

Rev. 00.11 — 30 January 2007

7 of 40

NXP Semiconductors

PCA2125

SPI Real time clock / calendar

6.2 Reset

The PCA2125 includes an internal reset circuit (see Figure 4) which is active whenever

the oscillator is stopped. The oscillator may be stopped, for example, by grounding one of

the oscillator pins, OSCI or OSCO. The oscillator is also considered to be stopped during

the time between power-up and stable crystal resonance. This time may be in the range of

200ms to 2s depending on crystal type, temperature and supply voltage. Whenever an

internal reset occurs, the RF flag is set.

The SPI interface is initialized whenever the chip enable line CE is inactive.

[1]

registers marked ‘x’ are undefined at power up and unchanged by subsequent resets.

[2]

registers marked ‘-’ are not implemented.

After reset, the following mode is entered:

32768Hz CLKOUT active

Fig 4.

Power on reset

Table 6:

Address

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

00HEX

control 1

000-

1000

01HEX

control 2

00000000

02HEX

seconds

xxxxxxx

03HEX

minutes

xxxxxxx

04HEX

hours

xxxxxx

05HEX

days

xxxxxx

06HEX

weekdays

-----x

07HEX

months

xxxxx

08HEX

years

xxxxxxxx

09HEX

minute alarm

xxxxxxx

0AHEX

hour alarm

xxxxxx

0BHEX

day alarm

xxxxxx

0CHEX

weekday alarm

----x

0DHEX

CLKOUT control

-----0

0EHEX

timer control

-----1

0FHEX

countdown timer

xxxxxxxx

001aaf897

chip in reset

chip not in reset

VDD

oscillation

internal

reset

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