ADS9316 datasheet(49/70 Pages) TI2

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7.2.5 Register 0Ch (Address = 0x0C) [Reset = 0x0000]

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Figure 7-7. Register 0Ch

RESERVED

PD_REF[1:0]

R/W-000000b

R/W-00b

RESERVED

CLK_PWR[2:0]

RESERVED

R/W-0b

R/W-000b

R/W-0000b

Table 7-11. Register 0Ch Field Descriptions

Bit

Field

Type

Reset

Description

15:10

RESERVED

R/W

000000b

Reserved. Do not change from the default reset value.

9:8

PD_REF[1:0]

R/W

00b

ADC reference voltage source selection.

00b = Normal device operation. Internal reference is active.

10b = Internal reference is active.

11b = Internal reference is inactive. Force an external reference via REFIO (pin 9).

RESERVED

R/W

Reserved. Do not change from the default reset value.

6:4

CLK_PWR[2:0]

R/W

000b

Control to select the power supply domain for the input clock.

000b = IOVDD domain.

101b = VDD_1V8 domain.

3:0

RESERVED

R/W

0000b

Reserved. Do not change from the default reset value.

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SBASAX4 – JUNE 2026

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