LAN9312 datasheet(142/458 Pages) SMSC

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High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

Revision 1.2 (04-08-08)

142

SMSC LAN9312

DATASHEET

10.2.2.3

I2C EEPROM Byte Read

Following the device addressing, a data byte may be read from the EEPROM by outputting a start

condition and control byte with a control code of 1010b, chip/block select bits as described in

Section 10.2.2.2, and the R/~W bit high. The EEPROM will respond with an acknowledge, followed by

8-bits of data. If the EEPROM slave fails to send an acknowledge, then the sequence is aborted and

the EPC_TIMEOUT bit in the EEPROM Command Register (E2P_CMD) is set. The I2C master then

sends a no-acknowledge, followed by a stop condition.

Figure 10.4 illustrates typical I2C EEPROM byte read for single and double byte addressing.

For a register level description of a read operation, refer to Section 10.2.1, "EEPROM Controller

Operation," on page 138.

10.2.2.4

I2C EEPROM Sequential Byte Reads

Following the device addressing, data bytes may be read sequentially from the EEPROM by outputting

a start condition and control byte with a control code of 1010b, chip/block select bits as described in

Section 10.2.2.2, and the R/~W bit high. The EEPROM will respond with an acknowledge, followed by

8-bits of data. If the EEPROM slave fails to send an acknowledge, then the sequence is aborted and

the EPC_TIMEOUT bit in the EEPROM Command Register (E2P_CMD) is set. The I2C master then

sends an acknowledge, and the EEPROM responds with the next 8-bits of data. This continues until

the last desired byte is read, at which point the I2C master sends a no-acknowledge, followed by a

stop condition.

Figure 10.4 illustrates typical I2C EEPROM sequential byte reads for single and double byte

addressing.

Figure 10.4 I2C EEPROM Byte Read

Figure 10.5 I2C EEPROM Sequential Byte Reads

S 1 0 1 0

Control Byte

S 1 0 1 0

Control Byte

Single Byte Addressing Read

Double Byte Addressing Read

0 0 0

Data Byte

R/~W

Chip / Block

Select Bits

R/~W

Chip / Block

Select Bits

S 1 0 1 0

Control Byte

S 1 0 1 0

Control Byte

Single Byte Addressing Sequential Reads

0 0 0

Data Byte

Double Byte Addressing Sequential Reads

...

R/~W

Chip / Block

Select Bits

R/~W

Chip / Block

Select Bits

...

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