LAN9312 datasheet(172/458 Pages) SMSC

172 / 458 page

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

Revision 1.2 (04-08-08)

172

SMSC LAN9312

DATASHEET

14.2.1

Interrupts

This section details the interrupt related System CSR’s. These registers control, configure, and monitor

the IRQ interrupt output pin and the various LAN9312 interrupt sources. For more information on the

LAN9312 interrupts, refer to Chapter 5, "System Interrupts," on page 49.

14.2.1.1

Interrupt Configuration Register (IRQ_CFG)

This read/write register configures and indicates the state of the IRQ signal.

Offset:

054h

Size:

32 bits

BITS

DESCRIPTION

TYPE

DEFAULT

31:24

Interrupt De-assertion Interval (INT_DEAS)

This field determines the Interrupt Request De-assertion Interval in multiples

of 10 microseconds.

Setting this field to zero causes the device to disable the INT_DEAS Interval,

reset the interval counter and issue any pending interrupts. If a new, non-

zero value is written to this field, any subsequent interrupts will obey the new

setting.

This field does not apply to the PME_INT interrupt.

R/W

00h

23:15

RESERVED

Interrupt De-assertion Interval Clear (INT_DEAS_CLR)

Writing a 1 to this register clears the de-assertion counter in the Interrupt

Controller, thus causing a new de-assertion interval to begin (regardless of

whether or not the Interrupt Controller is currently in an active de-assertion

interval).

0: Normal operation

1: Clear de-assertion counter

R/W

Interrupt De-assertion Status (INT_DEAS_STS)

When set, this bit indicates that interrupts are currently in a de-assertion

interval, and will not be sent to the IRQ pin. When this bit is clear, interrupts

are not currently in a de-assertion interval, and will be sent to the IRQ pin.

0: No interrupts in de-assertion interval

1: Interrupts in de-assertion interval

Master Interrupt (IRQ_INT)

This read-only bit indicates the state of the internal IRQ line, regardless of

the setting of the IRQ_EN bit, or the state of the interrupt de-assertion

function. When this bit is set, one of the enabled interrupts is currently

active.

0: No enabled interrupts active

1: One or more enabled interrupts active

11:9

RESERVED

IRQ Enable (IRQ_EN)

This bit controls the final interrupt output to the IRQ pin. When clear, the IRQ

output is disabled and permanently de-asserted. This bit has no effect on

any internal interrupt status bits.

0: Disable output on IRQ pin

1: Enable output on IRQ pin

R/W

7:5

RESERVED

LAN9312 Datasheet(PDF) 172 Page - SMSC Corporation

LAN9312 Datasheet(HTML) 172 Page - SMSC Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL