LAN9312 datasheet(174/458 Pages) SMSC

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High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

Revision 1.2 (04-08-08)

174

SMSC LAN9312

DATASHEET

14.2.1.2

Interrupt Status Register (INT_STS)

This register contains the current status of the generated interrupts. A value of 1 indicates the

corresponding interrupt conditions have been met, while a value of 0 indicates the interrupt conditions

have not been met. The bits of this register reflect the status of the interrupt source regardless of

whether the source has been enabled as an interrupt in the Interrupt Enable Register (INT_EN). Where

indicated as R/WC, writing a 1 to the corresponding bits acknowledges and clears the interrupt.

Offset:

058h

Size:

32 bits

BITS

DESCRIPTION

TYPE

DEFAULT

Software Interrupt (SW_INT)

This interrupt is generated when the SW_INT_EN bit of the Interrupt Enable

R/WC

Device Ready (READY)

This interrupt indicates that the LAN9312 is ready to be accessed after a

power-up or reset condition.

R/WC

1588 Interrupt Event (1588_EVNT)

This bit indicates an interrupt event from the IEEE 1588 module. This bit

should be used in conjunction with the 1588 Interrupt Status and Enable

event within the 1588 module.

Switch Fabric Interrupt Event (SWITCH_INT)

This bit indicates an interrupt event from the Switch Fabric. This bit should

be used in conjunction with the Switch Global Interrupt Pending Register

(SW_IPR) to determine the source of the interrupt event within the Switch

Fabric.

Port 2 PHY Interrupt Event (PHY_INT2)

This bit indicates an interrupt event from the Port 2 PHY. The source of the

interrupt can be determined by polling the Port x PHY Interrupt Source

Flags Register (PHY_INTERRUPT_SOURCE_x).

Port 1 PHY Interrupt Event (PHY_INT1)

This bit indicates an interrupt event from the Port 1 PHY. The source of the

interrupt can be determined by polling the Port x PHY Interrupt Source

Flags Register (PHY_INTERRUPT_SOURCE_x).

TX Stopped (TXSTOP_INT)

This interrupt is issued when STOP_TX bit in Transmit Configuration

R/WC

RX Stopped (RXSTOP_INT)

his interrupt is issued when the Host MAC receiver is halted.

R/WC

RX Dropped Frame Counter Halfway (RXDFH_INT)

This interrupt is issued when the Host MAC RX Dropped Frames Counter

80000000h).

R/WC

RESERVED

TX IOC Interrupt (TX_IOC)

This interrupt is generated when a buffer with the IOC flag set has been

fully loaded into the TX Data FIFO.

R/WC

RX DMA Interrupt (RXD_INT)

This interrupt is issued when the amount of data programmed in the RX

DMA Count (RX_DMA_CNT) field of the Receive Configuration Register

(RX_CFG) has been transferred out of the RX Data FIFO.

R/WC

LAN9312 Datasheet(PDF) 174 Page - SMSC Corporation

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