LAN9312 datasheet(175/458 Pages) SMSC

175 / 458 page

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

SMSC LAN9312

175

Revision 1.2 (04-08-08)

DATASHEET

GP Timer (GPT_INT)

This interrupt is issued when the General Purpose Timer Count Register

(GPT_CNT) wraps past zero to FFFFh.

R/WC

RESERVED

Power Management Interrupt Event (PME_INT)

This interrupt is issued when a Power Management Event is detected as

configured in the Power Management Control Register (PMT_CTRL). This

interrupt functions independent of the PME signal, and will still function if

the PME signal is disabled. Writing a '1' clears this bit regardless of the

state of the PME hardware signal. In order to clear this bit, all unmasked

bits in the Power Management Control Register (PMT_CTRL) must first be

cleared.

Note:

The Interrupt De-assertion interval does not apply to the PME

interrupt.

R/WC

TX Status FIFO Overflow (TXSO)

This interrupt is generated when the TX Status FIFO overflows.

R/WC

Receive Watchdog Time-out (RWT)

This interrupt is generated when a packet larger than 2048 bytes has been

received by the Host MAC.

Note:

This can occur when the switch engine adds a tag to a non-tagged

jumbo packet that is originally larger than 2044 bytes.

R/WC

Receiver Error (RXE)

Indicates that the Host MAC receiver has encountered an error. Please

refer to Section 9.9.5, "Receiver Errors," on page 136 for a description of

the conditions that will cause an RXE.

R/WC

Transmitter Error (TXE)

When generated, indicates that the Host MAC transmitter has encountered

an error. Please refer to Section 9.8.8, "Transmitter Errors," on page 131

for a description of the conditions that will cause a TXE.

R/WC

GPIO Interrupt Event (GPIO)

This bit indicates an interrupt event from the General Purpose I/O. The

source of the interrupt can be determined by polling the General Purpose

I/O Interrupt Status and Enable Register (GPIO_INT_STS_EN)

TX Data FIFO Underrun Interrupt (TDFU)

This interrupt is generated when the TX Data FIFO underruns.

R/WC

TX Data FIFO Overrun Interrupt (TDFO)

This interrupt is generated when the TX Data FIFO is full, and another write

is attempted.

R/WC

TX Data FIFO Available Interrupt (TDFA)

This interrupt is generated when the TX Data FIFO available space is

greater than the programmed level in the TX Data Available Level field of

the FIFO Level Interrupt Register (FIFO_INT).

R/WC

TX Status FIFO Full Interrupt (TSFF)

This interrupt is generated when the TX Status FIFO is full.

R/WC

TX Status FIFO Level Interrupt (TSFL)

This interrupt is generated when the TX Status FIFO reaches the

programmed level in the TX Status Level field of the FIFO Level Interrupt

R/WC

RX Dropped Frame Interrupt (RXDF_INT)

This interrupt is issued whenever a receive frame is dropped by the Host

MAC.

R/WC

BITS

DESCRIPTION

TYPE

DEFAULT

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