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LAN9312 Datasheet(PDF) 173 Page - SMSC Corporation |
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LAN9312 Datasheet(HTML) 173 Page - SMSC Corporation |
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173 / 458 page  High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 173 Revision 1.2 (04-08-08) DATASHEET Note 14.1 Register bits designated as NASR are not reset when either the SRST bit in the Hardware Configuration Register (HW_CFG) register or the DIGITAL_RST bit in the Reset Control Register (RESET_CTL) is set. 4 IRQ Polarity (IRQ_POL) When cleared, this bit enables the IRQ line to function as an active low output. When set, the IRQ output is active high. When the IRQ is configured as an open-drain output (via the IRQ_TYPE bit), this bit is ignored, and the interrupt is always active low. 0: IRQ active low output 1: IRQ active high output R/W NASR Note 14.1 0b 3:1 RESERVED RO - 0 IRQ Buffer Type (IRQ_TYPE) When this bit is cleared, the IRQ pin functions as an open-drain output for use in a wired-or interrupt configuration. When set, the IRQ is a push-pull driver. Note: When configured as an open-drain output, the IRQ_POL bit is ignored and the interrupt output is always active low. 0: IRQ pin open-drain output 1: IRQ pin push-pull driver R/W NASR Note 14.1 0b BITS DESCRIPTION TYPE DEFAULT |
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