LAN9312 datasheet(312/458 Pages) SMSC

312 / 458 page

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

Revision 1.2 (04-08-08)

312

SMSC LAN9312

DATASHEET

0853h

MAC_TX_PKTOK_CNT_1

Port 1 MAC Transmit OK Count Register, Section 14.5.2.27

0854h

MAC_RX_64_CNT_1

Port 1 MAC Transmit 64 Byte Count Register, Section 14.5.2.28

0855h

MAC_TX_65_TO_127_CNT_1

Port 1 MAC Transmit 65 to 127 Byte Count Register,

Section 14.5.2.29

0856h

MAC_TX_128_TO_255_CNT_1

Port 1 MAC Transmit 128 to 255 Byte Count Register,

Section 14.5.2.30

0857h

MAC_TX_256_TO_511_CNT_1

Port 1 MAC Transmit 256 to 511 Byte Count Register,

Section 14.5.2.31

0858h

MAC_TX_512_TO_1023_CNT_1

Port 1 MAC Transmit 512 to 1023 Byte Count Register,

Section 14.5.2.32

0859h

MAC_TX_1024_TO_MAX_CNT_1

Port 1 MAC Transmit 1024 to Max Byte Count Register,

Section 14.5.2.33

085Ah

MAC_TX_UNDSZE_CNT_1

Port 1 MAC Transmit Undersize Count Register,

Section 14.5.2.34

085Bh

RESERVED

Reserved for Future Use

085Ch

MAC_TX_PKTLEN_CNT_1

Port 1 MAC Transmit Packet Length Count Register,

Section 14.5.2.35

085Dh

MAC_TX_BRDCST_CNT_1

Port 1 MAC Transmit Broadcast Count Register,

Section 14.5.2.36

085Eh

MAC_TX_MULCST_CNT_1

Port 1 MAC Transmit Multicast Count Register,

Section 14.5.2.37

085Fh

MAC_TX_LATECOL_1

Port 1 MAC Transmit Late Collision Count Register,

Section 14.5.2.38

0860h

MAC_TX_EXCOL_CNT_1

Port 1 MAC Transmit Excessive Collision Count Register,

Section 14.5.2.39

0861h

MAC_TX_SNGLECOL_CNT_1

Port 1 MAC Transmit Single Collision Count Register,

Section 14.5.2.40

0862h

MAC_TX_MULTICOL_CNT_1

Port 1 MAC Transmit Multiple Collision Count Register,

Section 14.5.2.41

0863h

MAC_TX_TOTALCOL_CNT_1

Port 1 MAC Transmit Total Collision Count Register,

Section 14.5.2.42

0864-087Fh

RESERVED

Reserved for Future Use

0880h

MAC_IMR_1

Port 1 MAC Interrupt Mask Register, Section 14.5.2.43

0881h

MAC_IPR_1

Port 1 MAC Interrupt Pending Register, Section 14.5.2.44

0882h-0BFFh

RESERVED

Reserved for Future Use

Switch Port 2 CSRs

0C00h

MAC_VER_ID_2

Port 2 MAC Version ID Register, Section 14.5.2.1

0C01h

MAC_RX_CFG_2

Port 2 MAC Receive Configuration Register, Section 14.5.2.2

0C02h-0C0Fh

RESERVED

Reserved for Future Use

Table 14.12 Indirectly Accessible Switch Control and Status Registers (continued)

SYMBOL

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