DIO7416

Version 1.2, Sep 2025

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© 2025 Dioo Microcircuits Co., Ltd. Jiangsu

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Startup considerations with large capacitive load mismatches

Due to the FET based architecture of this translator, there are some considerations a designer must be

aware of during powering up with large differences in capacitance between the sides. If one supply

with smaller capacitance is already powered up, and the other is ramping (with EN pin high), the side

with the heavier load can ramp slower than the power supply ramp, due to only having an internal 10

kΩ pull up resistor. In this situation, once the rising POR threshold is met, the device enables all

circuitry. If the heavy capacitance side has not yet risen above about 70% of supply, the device

determines this as low, and briefly turns on the fall time accelerators to propagate a low. Once the fall

time accelerator has timed out, the signals rise and sit idle high.

This phenomenon can be eliminated by holding the EN pin low (disabled) until all supplies and buses

have ramped up, since this explicitly disables the bus acceleration circuitry until the bus has

completed power up. Slower supply ramps also help reduce this because the bus voltage follows the

supply closer if the ramp is slow.

10.3. Application curve