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AS1181 Datasheet(PDF) 29 Page - ams-OSRAM AG |
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AS1181 Datasheet(HTML) 29 Page - ams-OSRAM AG |
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29 / 92 page ![]() AS1181 Functional description Datasheet • PUBLIC • Document Feedback DS001139 • v3-00 • 2026-Apr-01 29 / 92 / 7.1.6.2 Staggering for the PWM mode with 2 PWM inputs If “td_stagger” field in register CH_DLY register (Address 0x1A24) is set to non-zero value, it applies as a delay in the illumination between channels group assigned to the STROBE_PWM1 input and a group assigned to the ID2_PWM2 input. Note that in this mode the grouping defined in the CH_GROUP register (Address 0x1A22) is ignored, the grouping follows “pwm_grp_split” field setting in register PWM_CTR register (Address 0x1A32). Figure 29: Stagger delay with 2 external PWM inputs |
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