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AS1181 Datasheet(PDF) 65 Page - ams-OSRAM AG |
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AS1181 Datasheet(HTML) 65 Page - ams-OSRAM AG |
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65 / 92 page  AS1181 Register description Datasheet • PUBLIC • Document Feedback DS001139 • v3-00 • 2026-Apr-01 65 / 92 / 8.3.22 CH_SLEW30 register (Address 0x1A2C) Table 34: CH_SLEW30 register (Write Access when system state == idle) Addr: 0x1A2C CH_SLEW30 Bit Bit field Default Access Bit description 15:0 Slew30 OTP RW Slew rate control for channel 0 to channel 3: Number of slew steps time and slew time, controlled by 4 bits per channel glob_slew_enable needs to be 1 to turn on channel slew / bit[3:0]..CH0, bit[7:4]..CH1, bit[11:8]..CH2, bit[15:12]..CH3 0 Slew time = 0µs, 1 step 1 Slew time = 0.3µs, 4 steps (100ns step time) 2 Slew time = 0.7µs, 8 steps (100ns step time) 3 Slew time = 0.6µs, 4 steps (200ns step time) 4 Slew time = 1.5µs, 16 steps (100ns step time) 5 Slew time = 1.4µs, 8 steps (200ns step time) 6 Slew time = 1.2µs, 4 steps (400ns step time) 7 Slew time = 3.0µs, 16 steps (200ns step time) 8 Slew time = 2.8µs, 8 steps (400ns step time) 9 Slew time = 2.4µs, 4 steps (800ns step time) |
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