AS1181 datasheet(35/92 Pages) AMSOSRAM

35 / 92 page

AS1181

Functional description

Datasheet • PUBLIC • Document Feedback

DS001139 • v3-00 • 2026-Apr-01

35 / 92

7.3

Interrupt controller

Interrupt requests are sent to output pin IRQ_N. This signal is active low and the pin is

configured as open drain output.

The condition to trigger an interrupt for a specific source is:

•

If an interrupt source is ASSERTED, ENABLED and NOT MASKED, then the IRQ_N is

asserted.

•

If an interrupt source is asserted, then it is captured in the interrupt status register

IRQ_STATUS0 register (Address 0x1AA4), IRQ_STATUS1 register (Address 0x1AA6)

and IRQ_STATUS2 register (Address 0x1AA8).

•

An interrupt is enabled if the corresponding enable register bit is set to 1 in the following

registers: IRQ_ENABLE0 register (Address 0x1A38), IRQ_ENABLE1 register (Address

0x1A3A) and IRQ_ENABLE2 register (Address 0x1A3C).

•

An interrupt can be masked (inhibited) if the corresponding mask register bit is set to 1 in

the following registers: IRQ_MASK0 register (Address 0x1AB0), IRQ_MASK1 register

(Address 0x1AB2), IRQ_MASK2 register (Address 0x1AB4).

•

IRQ_N is latched on the first interrupt occurrence.

•

IRQ_N is not cleared until all interrupt status registers containing a set interrupt are read

(reading the interrupt status registers clears them).

•

The IRQ_N output signal is the NOR-function of all interrupt sources.

AS1181 Datasheet(PDF) 35 Page - ams-OSRAM AG