High Density Programmable Logic

1

3192_08

Features

• HIGH-DENSITY PROGRAMMABLE LOGIC

— 192 I/O Pins

— 9000 PLD Gates

— 384 Registers

— High Speed Global Interconnect

— Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

— Small Logic Block Size for Random Logic

—

—

— TTL Compatible Inputs and Outputs

— Electrically Erasable and Reprogrammable

— Non-Volatile

— 100% Tested at Time of Manufacture

— Unused Product Term Shutdown Saves Power

• IN-SYSTEM PROGRAMMABLE

— Supports ISP™ or ispJTAG™ Programming

— Increased Manufacturing Yields, Reduced Time-to-

Market, and Improved Product Quality

— Reprogram Soldered Devices for Faster Debugging

• 100% IEEE 1149.1 BOUNDARY SCAN COMPATIBLE

• OFFERS THE EASE OF USE AND FAST SYSTEM

SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY

OF FIELD PROGRAMMABLE GATE ARRAYS

— Complete Programmable Device Can Combine Glue

Logic and Structured Designs

— Five Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control to Mini-

mize Switching Noise

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global

Interconnectivity

• ispDesignEXPERT™ – LOGIC COMPILER AND COM-

PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL

SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING

— Superior Quality of Results

— Tightly Integrated with Leading CAE Vendor Tools

— Productivity Enhancing Timing Analyzer, Explore

Tools, Timing Simulator and ispANALYZER™

— PC and UNIX Platforms

Functional Block Diagram

B0

B1

B2

B3

ORP

Global Routing Pool

C0

C1

C2

C3

F3

F2

F1

F0

E3

E2

E1

E0

Boundary

Scan

OR

Array

DQ

DQ

DQ

DQ

Twin

GLB

OR

Array

DQ

DQ

DQ

DQ

A0

A1

A2

A3

D3

D2

D1

D0

0139/3192

ORP

ORP

ORP

ORP

ORP

ORP

ORP

Description

The ispLSI 3192 is a High Density Programmable Logic

Device containing 384 Registers, 192 Universal I/O pins,

five Dedicated Clock Input Pins, twelve Output Routing

Pools (ORP), and a Global Routing Pool (GRP) which

allows complete inter-connectivity between all of these

elements. The ispLSI 3192 features 5-Volt in-system

programmability and in-system diagnostic capabilities.

The ispLSI 3192 offers non-volatile reprogrammability of

the logic, as well as the interconnect to provide truly

reconfigurable systems.

The basic unit of logic on the ispLSI 3192 device is the

Twin Generic Logic Block (Twin GLB) labelled A0, A1...F3.

There are a total of 24 of these Twin GLBs in the ispLSI

3192 device. Each Twin GLB has 24 inputs, a program-

mable AND array and two OR/Exclusive-OR Arrays, and

eight outputs which can be configured to be either com-

binatorial or registered. All Twin GLB inputs come from

the GRP.

Copyright © 2002 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

June 2002

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com