Specifications ispLSI 3192

12

Signal Locations and Descriptions

Dedicated Clock inputs. These clock inputs are connected to one of the

clock inputs of all the I/O cells in the device.

Dedicated Clock inputs. These clock inputs are connected to one of the

clock inputs of all the GLBs on the device.

Active Low (0) Reset pin which resets all of the GLB and I/O registers in

the device.

Input – Dedicated in-system programming enable input pin. When this

pin is high, the BSCAN TAP controller pins TMS, TDI, TDO and TCK

are enabled. When this pin is brought low, the ISP state machine

control pins MODE, SDI, SDO and SLCK are enabled. High-to-low

transition of this pin will put the device in the programming mode and

put all I/O pins in high-Z state.

Input - This pin performs two functions. It is the Test Data input pin

when ispEN is logic high. When ispEN is logic low, it functions as an

input pin to load programming data into the device. SDI is also used as

one of the two control pins for the isp state machine.

Input/Output Pins - These are the general purpose I/O pins used by the

logic array.

NAME

Table 2 - 0002/3192.BGA

BGA BALL NUMBERS

DESCRIPTION

I/O 0 - I/O 5

I/O 6 - I/O 11

I/O 12 - I/O 17

I/O 18 - I/O 23

I/O 24 - I/O 29

I/O 30 - I/O 35

I/O 36 - I/O 41

I/O 42 - I/O 47

I/O 48 - I/O 53

I/O 54 - I/O 59

I/O 60 - I/O 65

I/O 66 - I/O 71

I/O 72 - I/O 77

I/O 78 - I/O 83

I/O 84 - I/O 89

I/O 90 - I/O 95

I/O 96 - I/O 101

I/O 102 - I/O 107

I/O 108 - I/O 113

I/O 114 - I/O 119

I/O 120 - I/O 125

I/O 126 - I/O 131

I/O 132 - I/O 137

I/O 138 - I/O 143

I/O 144 - I/O 149

I/O 150 - I/O 155

I/O 156 - I/O 161

I/O 162 - I/O 167

I/O 168 - I/O 173

I/O 174 - I/O 179

I/O 180 - I/O 185

I/O 186 - I/O 191

Global Output Enable input pins.

K17 and J20

GOE0 and GOE1

M1

RESET

M3, M2, L20

Y0, Y1 and Y2

K20, K18

Y3 and Y4

L4

BSCAN/ispEN2

L3

TDI/SDI2

L2

TCK/SCLK2

L1

TMS/MODE2

J18

TRST/NC1, 2

K1

TDO/SDO2

Output - This pin performs two functions. When ispEN is logic low, it

functions as the pin to read the isp data. When ispEN is high it functions

as Test Data Out.

Input - Test Reset, active low to reset the Boundary Scan State

Machine.

Input - This pin performs two functions. It is the Test Mode Select input

pin when ispEN is logic high. When ispEN is logic low, it functions as

pin to control the operation of the isp state machine.

Input - This pin performs two functions. It is the Test Clock input pin

when ispEN is logic high. When ispEN is logic low, it functions as a

clock pin for the Serial Shift Register.

Test output enable pin. TOE tristates all I/O pins when a logic low is

driven.

J19

TOE

Ground (GND)

GND

V

VCC

CC

M4,

N1,

N2,

N3,

P1,

P2

P3,

R2,

T1,

P4,

R3,

T2

T3,

U2,

V1,

T4,

U3,

V2

V3,

W2,

Y1,

W3,

Y2,

W4

U5,

Y3,

Y4,

V5,

W5,

Y5

U7,

W6,

Y6,

V7,

W7,

Y7

V8,

W8,

Y8,

U9,

V9,

W9

W10, V10,

Y10,

Y11, W11,

V11

U11,

Y12,

W12, V12, U12,

Y13

V13,

Y14,

W14, Y15, V14,

W15

Y16,

U14,

V15,

W16, Y17,

V16

Y18,

U16,

V17,

W18, Y19,

V18

Y20,

W20, V19,

U19, U18,

T17

U20,

T18,

T19,

T20, R18,

P17

R20,

P18,

P19,

P20, N18,

N19

M17, M18, M19, M20, L19,

L18

J17,

H20,

H19,

H18, G20,

G19

G18,

F19,

E20,

G17, F18,

E19

E18,

D19,

C20,

E17, D18,

C19

C18,

B19,

A20,

A19, B18,

B17

D16,

A18,

A17,

C16, B16,

A16

D14,

B15,

A15,

C14, B14,

A14

C13,

B13,

A13,

D12, C12,

B12

B11,

C11,

A11,

A10, B10,

C10

D10,

A9,

B9,

C9,

D9,

A8

C8,

A7,

B7,

A6,

C7,

B6

A5,

D7,

C6,

B5,

A4,

C5

A3,

D5,

C4,

B3,

B2,

A2

C3,

B1,

C2,

D2,

D3,

E4

D1,

E3,

E2,

E1,

F3,

G4

F1,

G3,

G2,

G1,

H3,

H2

J4,

J3,

J2,

J1,

K2,

K3

A1, D4, D8, D13, D17, H4, H17, J9, J10,

J11, J12, K9, K10, K11, K12, L9, L10, L11,

L12, M9, M10, M11, M12, N4, N17, U4, U8,

U13, U17

D6, D11, D15, F4, F17, K4, L17, R4, R17,

U6, U10, U15

No Connect

NC

A12, B4, B8, B20, C1, C15, C17, D20, F2,

F20, H1, K19, N20, R1, R19, U1, V4, V6,

V20, W1, W13, W17, W19, Y9

1. NC pins are not to be connected to any active signal, Vcc or GND.

2. Pins have dual function capability.