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TSZ22111

• 15 • 001

BU21180FS

TSZ02201-0L5L0F300930-1-2

06.Aug.2018 Rev.002

2-wire Serial Bus Protocol

Write Protocol

S

A

6

S

A

5

S

A

4

S

A

3

S

A

2

S

A

1

S

A

0

R

A

6

R

A

5

R

A

4

R

A

3

R

A

2

R

A

1

R

A

0

R

A

7

W

D

6

W

D

5

W

D

4

W

D

3

W

D

2

W

D

1

W

D

0

W

D

7

W

D

6

W

D

5

W

D

4

W

D

3

W

D

2

W

D

1

W

D

0

W

D

7

S

T

A

R

T

W

R

T

E

A

C

K

A

C

K

A

C

K

A

C

K

Slave

Address with

Write Bit

Register

Address

Write Data[0]

Write Data[1]

1

2

3

4

4

W

D

6

W

D

5

W

D

4

W

D

3

W

D

2

W

D

1

W

D

0

W

D

7

A

C

K

Write Data[n]

4

S

T

O

P

5

controlled by HOST

controlled by BU21180FS

I

Figure 9. 2-wire Serial Bus Write Protocol

1: The communication starts when IC received the START condition.

2: IC transmits ACK signal when 7-bit slave address and write bit are received. IC carries out processing by MPU after the

transmission of ACK signal. Clock stretch is carried out during the processing.

3: IC transmits ACK signal when 8-bit write register address are received. IC carries out processing by MPU after the

transmission of ACK signal. Clock stretch is carried out during the processing.

4: IC transmits ACK signal when 8-bit write data are received. IC carries out processing by MPU after the transmission of

ACK signal. Clock stretch is carried out during the processing. IC supports sequential write. So the register address is

incremented, and the next of 0xFF becomes 0x00.

5: The communication finishes when IC received the STOP condition.

Read Protocol

S

A

6

S

A

5

S

A

4

S

A

3

S

A

2

S

A

1

S

A

0

R

A

6

R

A

5

R

A

4

R

A

3

R

A

2

R

A

1

R

A

0

R

A

7

S

T

A

R

T

W

R

T

E

A

C

K

A

C

K

A

C

K

A

C

K

Slave

Address with

Write Bit

Register

Address

Read Data[0]

1

2

3

5

controlled by HOST

S

A

6

S

A

5

S

A

4

S

A

3

S

A

2

S

A

1

S

A

0

S

T

A

R

T

Slave

Address with

Read Bit

4

R

D

6

R

D

5

R

D

4

R

D

3

R

D

2

R

D

1

R

D

0

R

D

7

6

R

E

A

D

Read Data[1]

R

D

6

R

D

5

R

D

4

R

D

3

R

D

2

R

D

1

R

D

0

R

D

7

6

7

N

A

C

K

S

T

O

P

I

controlled by BU21180FS

Figure 10. 2-wire Serial Bus Read Protocol

1: The communication starts when IC received the START condition.

2: IC transmits ACK signal when 7-bit slave address and write bit are received. IC carries out processing by MPU after the

transmission of ACK signal. Clock stretch is carried out during the processing.

3: IC transmits ACK signal when 8-bit read register address are received. IC carries out processing by MPU after the

transmission of ACK signal. Clock stretch is carried out during the processing.

4: The communication continues when IC received start condition signal.

5: IC transmits ACK signal when 7-bit slave address and read bit are received. IC carries out processing by MPU after the

transmission of ACK signal. Clock stretch is carried out during the processing.

6: IC transmits read data every clock is received until NACK signal. IC carries out processing by MPU after receiving

ACK or NACK signal. Clock stretch is carried out during the processing. IC supports sequential read. So the register

address is incremented, and the next of 0xFF becomes 0x00.

7: The communication finishes when IC received the STOP condition.