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BU21180FS Datasheet(PDF) 28 Page - Rohm

Part # BU21180FS
Description  Capacitive Switch Controller IC
PDF  43 Pages
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Manufacturer  ROHM [Rohm]
Direct Link  http://www.rohm.com
Logo ROHM - Rohm

BU21180FS Datasheet(HTML) 28 Page - Rohm

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© 2017 ROHM Co., Ltd. All rights reserved.
www.rohm.com
TSZ22111
• 15 • 001
BU21180FS
TSZ02201-0L5L0F300930-1-2
06.Aug.2018 Rev.002
0xA2-0xA3: Unexpected Long Press Detection Time
Name:
TIME_UNKNOWN_CFG
Address:
0xA2-0xA3
Description:
These registers configure the time until detecting unexpected long press. The data 1 is set to the register
“Unexpected Long Press Detection” when unexpected long press is detected. Until unexpected long press is
avoided, the unexpected long press is repeatedly detected each configured time.
The time until detecting unexpected long press = TIME_UNKNOWN_*[7:0] x Approximately 1s
In the case TIME_ UNKNOWN_*[7:0] is set to 0, unexpected long press are not detected.
* represent the setting number A and B.
Address
R/W
Initial
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0xA2
R/W
0x00
TIME_UNKNOWN_A[7:0]
0xA3
R/W
0x00
TIME_UNKNOWN_B[7:0]
0xA4-0xB1: Long Press Detection Time / Repeated Long Press Detection Time
Name:
TIME_HLD_CFG
Address:
0xA4-0xB1
Description:
Pressing the switch for a fixed time is referred
to as “long press”. After first long press is detected,
subsequent long pressing is
referred to as “repeated long press”. These registers configure the time until
detecting long press and repeated long press. The data 1 is set to the register
“Switch Long Press Detection”
when long press is detected. And t
he data 1 is set to the register “Switch Repeated Long Press Detection”
when repeated long press is detected.
The time until detecting long press = TIME_HLD_*[7:0] x Approximately 0.1s
In the case TIME_HLD_*[7:0] is set to 0, long press are not detected.
The time until detecting repeated long press = TIME_HLD_RPT_*[7:0] x Approximately 0.1s
In the case TIME_HLD_RPT_*[7:0] is set to 0, repeated long press is not detected.
* represent the setting number from A to G.
Address
R/W
Initial
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0xA4
R/W
0x00
TIME_HLD_A[7:0]
0xA5
R/W
0x00
TIME_HLD_RPT_A[7:0]
0xA6
R/W
0x00
TIME_HLD_B[7:0]
0xA7
R/W
0x00
TIME_HLD_RPT_B[7:0]
0xA8
R/W
0x00
TIME_HLD_C[7:0]
0xA9
R/W
0x00
TIME_HLD_RPT_C[7:0]
0xAA
R/W
0x00
TIME_HLD_D[7:0]
0xAB
R/W
0x00
TIME_HLD_RPT_D[7:0]
0xAC
R/W
0x00
TIME_HLD_E[7:0]
0xAD
R/W
0x00
TIME_HLD_RPT_E[7:0]
0xAE
R/W
0x00
TIME_HLD_F[7:0]
0xAF
R/W
0x00
TIME_HLD_RPT_F[7:0]
0xB0
R/W
0x00
TIME_HLD_G[7:0]
0xB1
R/W
0x00
TIME_HLD_RPT_G[7:0]



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