ADATE320 datasheet(15/78 Pages) AD

15 / 78 page

Data Sheet

ADATE320

SPECIFICATIONS

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Rev. C | 15 of 78

Table 7.

Parameter

Min

Typ

Max

Unit

Test Level

Test Conditions/Comments

Range A

−1.0

+4.0

Range B, Range C, Range D, and

Range E

−1.5

+4.5

Zero-Current Offset

Range B

−4

%FSR

Interpolated from measurements sourcing and sinking

80% FS current each range; for example, 2% FSR is 40

µA in Range B

All Ranges

±0.5

%FSR

Zero-Current Offset TC

Range A

±0.01

%FSR/°C

Range B, Range C, and Range D

±0.01

%FSR/°C

Range E

±0.02

%FSR/°C

Gain Error

Derived from measurements sourcing and sinking 80%

FS current

Range B

−30

All Ranges

−10

Gain TC

Range A

±50

ppm/°C>

Range B, Range C, and Range D

±50

ppm/°C

Range E

±50

ppm/°C

INL

After two-point gain/offset calibration at ±80% FS current

Range A

±0.02

%FSR

Measured over FSR output of −40 mA to +40 mA

Range B

−0.02

+0.02

%FSR

Measured over FSR output of −1 mA to +1 mA

Range C, Range D, and Range E

±0.01

%FSR

Measured over FSR output of Range C, Range D, and

Range E

DUTx Pin Voltage Rejection

−1.3

+1.3

µA

Range B, FVMI, force −1.0 V and +4.0 V into 0.5 mA

load, measure ∆I reported at PPMU_Mx pin

DUTGND Voltage Accuracy

−5

±1

Over ±0.1 V range

MEASURE PIN DC

CHARACTERISTICS

Output Range

−1.5

+5.0

Output Impedance

200

PPMU enabled in FVMV, source resistance: PPMU force

4.5 V into 0.0 mA, −1.0 mA, sink resistance: PPMU

force −1.5 V into 0.0 mA, 1.0 mA, resistance = ∆V/∆I at

PPMU_Mx pin

Output Leakage Current When

Tristated

−1

µA

Tested at −1.7 V and +5.2 V

Output Short Circuit Current

−10

+10

PPMU enabled in FVMV, source: PPMU force +4.5

V, PPMU_Mx = −1.5 V, sink: PPMU force −1.5 V,

PPMU_Mx = 5.0 V

PPMU_Mx Pin, Parasitic Output

Capacitance

Parasitic capacitance contributed by pin

PPMU_Mx Pin, External Load

Capacitance

100

External capacitance tolerated by pin (exceeding this

value may cause instability)

PPMU VOLTAGE CLAMPS (FI)

PPMU enabled in FIMI, PPMU clamps enabled; clamp

accuracy applies only when |PCHx − PCLx| ≥ 1.0 V

Low Voltage Clamp Range (PCLx)

−1.5

+3.5

High Voltage Clamp Range (PCHx)

−0.5

+4.5

Offset, Voltage Clamps (PCHx/PCLx) −300

+300

Range B, PPMU force ±0.5 mA into open; PCHx

measured at DAC Code 0x4000 (0.0 V) with PCLx at

DAC Code 0x0000 (−2.5 V); PCLx measured at DAC

ADATE320 Datasheet(PDF) 15 Page - Analog Devices

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