BQ24151YFFR datasheet(5/39 Pages) TI

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bq24150

bq24151

www.ti.com ...................................................................................................................................................................................................... SLUS824 – JUNE 2008

ELECTRICAL CHARACTERISTICS (continued)

Circuit of Figure 1, VBUS = 5 V, HZ_MODE = 0, OPA_MODE = 0 (charger mode operation), TJ = 0°C to 125°C, TJ = 25°C for

typical values (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

INPUT CURRENT LIMITING

IIN = 100 mA

IIN

Input current limiting threshold

USB charge mode

IIN = 500 mA

450

475

500

VREF BIAS REGULATOR

VBUS >VIN(min) or V(AUXPWR) > V(BAT)min,

Vref

Internal bias regulator voltage

6.5

I(VREF) = 1 mA, C(VREF) = 1

µF

Vref output short current limit

Voltage from BOOT pin to SW

During charge or boost operation

6.5

BATTERY RECHARGE THRESHOLD

V(RCH)

Recharge threshold voltage

Below V(OREG)

100

120

150

V(AUXPWR) decreasing below threshold,

Deglitch time

130

tFALL = 100 ns, 10-mV overdrive

STAT OUTPUTS

Low-level output saturation

IO = 10 mA, sink current

0.4

voltage, STAT

VOL(STAT)

High-level leakage current for

Voltage on STAT pin is 5 V

µA

STAT

I2C BUS LOGIC LEVELS AND TIMING CHARACTERISTICS

VOL

Output low threshold level

IO = 10 mA, sink current

0.4

VIL

Input low threshold level

0.4

VIH

Input high threshold level

1.2

I(BIAS)

Input bias current

V(pull-up) = 1.8 V, SDA and SCL

µA

f(SCL)

SCL clock frequency

3.4

MHz

BATTERY DETECTION

Battery detection current before

Begins after termination detected,

–0.45

charge done (sink current) (1)

V(AUXPWR) ≤ V(OREG)

I(DETECT)

Battery detection time

262

SLEEP COMPARATOR

Sleep-mode entry threshold,

V(SLP)

2.3 V

≤ V(AUXPWR) ≤ V(OREG), VBUS falling

+0.0

+0.04

+0.1

VBUS - VAUXPWR

Sleep-mode exit hysteresis

2.3 V

≤ V(AUXPWR) ≤ V(OREG)

100

160

V(SLP_EXIT)

Deglitch time for VBUS rising

Rising voltage, 2-mV overdrive, tRISE = 100 ns

above V(SLP) + V(SLP_EXIT)

UNDERVOLTAGE LOCKOUT

UVLO

IC active threshold voltage

VBUS rising

3.05

3.3

3.55

UVLO(HYS)

IC active hysteresis

VBUS falling from above UVLO

120

150

PWM

Internal top reverse blocking

IIN(LIMIT) = 500 mA, Measured from VBUS to

180

250

MOSFET on-resistance

PMID

Internal top N-channel Switching

Measured from PMID to SW

120

250

Ω

MOSFET on-resistance

Internal bottom N-channel

Measured from SW to PGND

150

200

MOSFET on-resistance

f(OSC)

Oscillator frequency

MHz

Frequency accuracy

–10%

10%

D(MAX)

Maximum duty cycle

99.5%

D(MIN)

Minimum duty cycle

Synchronous mode to

non-synchronous mode transition

Low side MOSFET cycle by cycle current sensing

100

current threshold(2)

(1)

Negative charge current means the charge current flows from the battery to charger (discharging battery).

(2)

Bottom N-channel MOSFET always turns on for

≈60 ns and then turns off if current is too low.

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