POWERDOWN

CHARGE

CONFIGURE

BOOST

CONFIGURE

BOOST

HIGH

IMPEDANCE

SHORT

CIRCUIT

PWMCHARGE

(bq24150)

NOFAULTS

HZ_MODE=1

OPA_MODE=1

HZ_MODE=0

orFAULTS

orFAULTS

V

START UP

NoFAULTS

HZ_MODE=1

Or

OPA_MODE=0

orFAULTS

OPA_MODE=1

HZ_MODE=0

HZ_MODE=1

or

OPA_MODE=1

HZ_MODE=0

HZ_MODE=1

HZ_MODE=0, OPA_MODE=0

NOFAULTS

OPA_MODE=0

ANY STATE

SERIAL INTERFACE DESCRIPTION

F/S Mode Protocol

bq24150

bq24151

Figure 26. State Diagram for bq24150/1

January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the

through open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signal

processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The

master also generates specific conditions that indicate the START and STOP of data transfer. A slave device

receives and/or transmits data on the bus under control of the master device.

The bq24150/1 device works as a slave and supports the following data transfer modes, as defined in the

in write mode). The interface adds flexibility to the battery charge solution, enabling most functions to be

programmed to new values depending on the instantaneous application requirements. Register contents remain

intact as long as supply voltage remains above 2.2 V (typical).

The data transfer protocol for standard and fast modes is exactly the same; therefore, they are referred to as the

F/S-mode in this document. The protocol for high-speed mode is different from the F/S-mode, and it is referred to

as the HS-mode. The bq24150/1 device only supports 7-bit addressing. The device 7-bit address is defined as

‘1101011’ (6BH).

The master initiates data transfer by generating a start condition. The start condition is when a high-to-low

recognize a start condition.

Copyright © 2008, Texas Instruments Incorporated

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