STARTCondition

DATA

CLK

STOP Condition

S

P

DATA

CLK

DataLine

Stable;

DataValid

Change

ofData

Allowed

bq24150

bq24151

Figure 27. START and STOP Condition

The master then generates the SCL pulses, and transmits the 8-bit address and the read/write direction bit R/W

on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires

the SDA line to be stable during the entire high period of the clock pulse (see Figure 28). All devices recognize

the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a

matching address generates an acknowledge (see Figure 28) by pulling the SDA line low during the entire high

period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that communication link with a

slave has been established.

Figure 28. Bit Transfer on the Serial Interface

The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from the

slave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. So an

acknowledge signal can either be generated by the master or by the slave, depending on which one is the

receiver. the 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as

necessary. To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line

from low to high while the SCL line is high (see Figure 30). This releases the bus and stops the communication

stop condition, all devices know that the bus is released, and wait for a start condition followed by a matching

address. If a transaction is terminated prematurely, the master needs sending a STOP condition to prevent the

section will result in FFh being read out.

24

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