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MIC5013 Datasheet(PDF) 3 Page - Micrel Semiconductor |
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MIC5013 Datasheet(HTML) 3 Page - Micrel Semiconductor |
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3 / 15 page ![]() July 2005 3 MIC5013 MIC5013 Micrel, Inc. Electrical Characteristics (Note 3, 5) Test circuit. TA = –55°C to +125°C, V+ = 15V, all switches open, unless otherwise specified. Parameter Conditions Min Typical Max Units Supply Current, I7 V+ = 32V VIN = 0V, S4 closed 0.1 10 µA VIN = VS = 32V 8 20 mA Logic Input Voltage, VIN V+ = 4.75V Adjust VIN for VGATE low 2 V Adjust VIN for VGATE high 4.5 V V+ =15V Adjust VIN for VGATE high 5.0 V Logic Input Current, I1 V+ = 32V VIN = 0V –1 µA VIN = 32V 1 µA Input Capacitance Pin 1 5 pF Gate Drive, VGATE S1, S2 closed, V+ = 7V, I6 = 0 13 15 V VS = V+, VIN = 5V V+ = 15V, I6 = 100 µA 24 27 V Zener Clamp, S2 closed, VIN = 5V V+ = 15V, VS = 15V 11 12.5 15 V VGATE – VSOURCE V+ = 32V, VS = 32V 11 13 16 V Gate Turn-on Time, tON VIN switched from 0 to 5V; measure time 60 200 µs (Note 4) for VGATE to reach 20V Gate Turn-off Time, tOFF VIN switched from 5 to 0V; measure time 4 10 µs for VGATE to reach 1V Threshold Bias Voltage, V2 I2 = 200 µA 1.7 2 2.2 V Current Sense Trip Voltage, S2 closed, VIN = 5V, V+ = 7V, S4 closed 75 105 135 mV VSENSE – VSOURCE Increase I3 I2 = 100 µA VS = 4.9V, S4 open 70 100 130 mV V+ = 15V S4 closed 150 210 270 mV I2 = 200 µA VS = 11.8V, S4 open 140 200 260 mV V+ = 32V VS = 0V, S4 open 360 520 680 mV I2 = 500 µA VS = 25.5V, S4 open 350 500 650 mV Peak Current Trip Voltage, S3, S4 closed, 1.6 2.1 V VSENSE – VSOURCE V+ = 15V, VIN = 5V Fault Output Voltage, V8 VIN = 0V, I8 = –100 µA 0.4 1 V VIN = 5V, I8 = 100 µA, current sense tripped 14 14.6 V Note 1. Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Electrical specifications do not apply when operating the device beyond its specified Operating Ratings. Note 2. The MIC5010 is ESD sensitive. Note 3. Minimum and maximum Electrical Characteristics are 100% tested at TA = 25°C and TA = 85°C, and 100% guaranteed over the entire range. Typicals are characterized at 25°C and represent the most likely parametric norm. Note 4. Test conditions reflect worst case high-side driver performance. Low-side and bootstrapped topologies are significantly faster—see Applications Information. Note 5. Specification for packaged product only. |
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