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V54C3256804VT Datasheet(PDF) 18 Page - Mosel Vitelic, Corp |
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V54C3256804VT Datasheet(HTML) 18 Page - Mosel Vitelic, Corp |
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18 / 52 page ![]() 18 V54C3256(16/80/40)4V(T/S/B) Rev. 1.6 September 2002 MOSEL VITELIC V54C3256(16/80/40)4V(T/S/B) AC Characteristics 1,2, 3 TA = 0 to 70 °C; VSS = 0 V; VDD = 3.3 V ± 0.3 V, tT = 1 ns # Symbol Parameter Limit Values Unit Note -6 -7PC -7 -8PC Min. Max. Min. Max. Min. Max. Min. Max. Clock and Clock Enable 1tCK Clock Cycle Time CAS Latency = 3 CAS Latency = 2 6 7.5 – – 7 7.5 – – 7 10 – – 8 10 – – s ns ns 2tCK Clock Frequency CAS Latency = 3 CAS Latency = 2 – – 166 133 – – 143 133 – – 143 100 – – 125 100 MHz MHz 3tAC Access Time from Clock CAS Latency = 3 CAS Latency = 2 – _ 5.4 5.4 – _ 5.4 5.4 – _ 5.4 6 – _ 6 6 ns ns 2, 4 4tCH Clock High Pulse Width 2.5 – 2.5 – 2.5 –3–ns 5tCL Clock Low Pulse Width 2.5 – 2.5 – 2.5 –3–ns 6tT Transition Tim 0.3 1.2 0.3 1.2 0.3 1.2 0.5 10 ns Setup and Hold Times 7tIS Input Setup Time 1.5 – 1.5 – 1.5 –2–ns 5 8tIH Input Hold Time 0.8 – 0.8 – 0.8 –1–ns 5 9tCKS Input Setup Time 1.5 – 1.5 – 1.5 –2–ns 5 10 tCKH CKE Hold Time 0.8 – 0.8 – 0.8 –1–ns 5 11 tRSC Mode Register Set-up Time 12 – 14 – 14 – 16 – ns 12 tSB Power Down Mode Entry Time 0 6 0 7 0 708ns Common Parameters 13 tRCD Row to Column Delay Time 12 – 15 – 15 – 20 – ns 6 14 tRP Row Precharge Time 15 – 15 – 15 – 20 – ns 6 15 tRAS Row Active Time 40 100K 42 100K 42 100K 45 100k ns 6 16 tRC Row Cycle Time 60 – 60 – 60 – 60 – ns 6 17 tRRD Activate(a) to Activate(b) Command Period 12 – 14 – 14 – 16 – ns 6 18 tCCD CAS(a) to CAS(b) Command Period 1 – 1 – 1 – 1 – CLK Refresh Cycle 19 tREF Refresh Period (8192 cycles) — 64 — 64 — 64 — 64 ms 20 tSREX Self Refresh Exit Time 1 — 1 — 1 — 1 — CLK |
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