XMEGAA datasheet(45/375 Pages) ATMEL

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8077B–AVR–06/08

XMEGA A

5.13

5.13.1

CTRL - DMA Control Register

• Bit 7 - ENABLE: DMA Enable

Setting this bit enables the DMA Controller. If the DMA Controller is enabled and this bit is writ-

ten to zero, the ENABLE bit is not cleared before the internal transfer buffer is empty and the

DMA data transfer is aborted.

• Bit 6 - RESET: DMA Software Reset

Setting this bit enables the software reset. This bit is automatically cleared when reset is com-

pleted. This bit can only be set when the DMA Controller is disabled (ENABLE = 0).

• Bit 5:4 - Res: Reserved

These bits are unused and reserved for future use. For compatibility with future devices, always

write these bits to zero when this register is written.

• Bit 3:2 - DBUFMODE[1:0]: DMA Double Buffer Mode

These bits enables the double buffer on the different channels according to Table 5-1.

• Bit 1:0 - PRIMODE[1:0]: DMA Channel Priority Mode

These bits determine the internal channel priority according to Table 5-2.

Bit

76543210

+0x00

ENABLE

RESET

DBUFMODE[1:0]

PRIMODE[1:0]

CTRL

Read/Write

R/W

Initial Value

00000000

Table 5-1.

DMA Double Buffer settings

DBUFMODE[1:0]

Group Configuration

Description

DISABLED

No double buffer enabled

CH01

Double buffer enabled on channel0/1

CH23

Double buffer enabled on channel2/3

CH01CH23

Double buffer enabled on channel0/1 and channel2/3

Table 5-2.

DMA Channel Priority settings

PRIMODE[1:0]

Group Configuration

Description

RR0123

Round Robin

CH0RR123

Channel0 > Round Robin (Channel 1, 2 and 3)

CH01RR23

Channel0 > Channel1 > Round Robin (Channel 2 and

CH0123

Channel0 > Channel1 > Channel2 > Channel3

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