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XMEGAA Datasheet(PDF) 49 Page - ATMEL Corporation

Part # XMEGAA
Description  8-bit XMEGAA Microcontroller
PDF  375 Pages
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Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

XMEGAA Datasheet(HTML) 49 Page - ATMEL Corporation

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49
8077B–AVR–06/08
XMEGA A
• Bit [3:2] - ERRINTLVL[1:0]: DMA Channel Error Interrupt Level
These bits enable the interrupt for DMA channel transfer error select the interrupt level as
described in ”Interrupts and Programmable Multi-level Interrupt Controller” on page 108. The
enabled interrupt will trigger for the conditions when the ERRIF is set.
• Bit [1:0] - TRNINTLVL[1:0]: DMA Channel Transaction Complete Interrupt Level
These bits enable the interrupt for DMA channel transaction complete and select the interrupt
level as described in ”Interrupts and Programmable Multi-level Interrupt Controller” on page 108.
The enabled interrupt will trigger for the conditions when the TRNIF is set.
5.14.3
ADDRCTRL - DMA Channel Address Control Register
• Bit 7:6 - SRCRELOAD[1:0]: DMA Channel Source Address Reload
These bits decide the DMA channel source address reload according to Table 5-4. These bits
can not be changed if the channel is busy.
• Bit 5:4 - SRCDIR[1:0]: DMA Channel Source Address Mode
These bits decide the DMA channel source address mode according to Table 5-5. These bits
can not be changed if the channel is busy.
• Bit 3:2 - DESTRELOAD[1:0]: DMA Channel Destination Address Reload
These bits decide the DMA channel destination address reload according to Table 5-6 on page
50. These bits can not be changed if the channel is busy.
Bit
7
6
5432
10
+0x02
SRCRELOAD[1:0]
SRCDIR[1:0]
DESTRELOAD[1:0]
DESTDIR[1:0]
ADDRCTRL
Read/Write
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
Initial Value
0
0
0000
00
Table 5-4.
DMA channel source address reload settings
SRCRELOAD[1:0]
Group Configuration
Description
00
NONE
No reload performed.
01
BLOCK
DMA source address register is reloaded with initial
value at end of each block transfer.
10
BURST
DMA source address register is reloaded with initial
value at end of each burst transfer.
11
TRANSACTION
DMA source address register is reloaded with initial
value at end of each transaction.
Table 5-5.
DMA channel source address mode settings
SRCDIR[1:0]
Group Configuration
Description
00
FIXED
Fixed.
01
INC
Increment.
10
DEC
Decrement.
11
-
Reserved



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