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XMEGAA Datasheet(PDF) 46 Page - ATMEL Corporation |
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XMEGAA Datasheet(HTML) 46 Page - ATMEL Corporation |
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46 / 375 page  46 8077B–AVR–06/08 XMEGA A 5.13.2 INTFLAGS - DMA Interrupt Status Register • Bit 7:4 - CHnERRIF[3:0]: DMA Channel n Error Interrupt Flag If an error condition is detected on DMA channel n, the CHnERRIF flag will be set. Writing a one to this bit location will clear the flag. • Bit 3:0 - CHnTRNFIF[3:0]: DMA Channel n Transaction Complete Interrupt Flag When a transaction on channel n has been completed, the CHnTRFIF flag will set. If unlimited repeat count is enabled, this flag is read as one after each block transfer. Writing a one to this bit location will clear the flag. 5.13.3 STATUS - DMA Status Register • Bit 7:4 - CHnBUSY[3:0]: DMA Channel Busy When channel n starts a DMA transaction, the CHnBUSY flag will be read as one. This flag is automatically cleared when the DMA channel is disabled, when the Channel n transaction Com- plete Interrupt Flag is set or if the DMA Channel n Error Interrupt flag is set. • Bit 3:0 - CHnPEND[3:0]: DMA Channel Pending If a block transfer is pending on DMA channel n, the CHnPEND flag will be read as one. This flag is automatically cleared when the block transfer starts, or if the transfer is aborted. 5.13.4 TEMPH - DMA Temporary Register High • Bit 7:0 - TEMP[7:0]: DMA Temporary Register This register is used when reading and writing 24-bit registers in the DMA controller. Byte 2 of the 24-bit register is stored when it is written by the CPU. Byte 2 of the 24-bit register is stored here when byte 1 is read by the CPU. This register can also be read and written from the user software. Reading and writing 24-bit register requires special attention, for details refer to ”Accessing 16- bits Registers” on page 12. Bit 765 4 3 2 1 0 +0x04 CH3ERRIF CH2ERRIF CH1ERRIF CH0ERRIF CH3TRNFIF CH2TRNFIF CH1TRNFIF CH0TRNFIF INTFLAGS Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 543 210 +0x05 CH3BUSY CH2BUSY CH1BUSY CH0BUSY CH3PEND CH2PEND CH1PEND CH0PEND STATUS Read/Write R RRR RRR R Initial Value 0 0 0 0 0 0 0 0 Bit 7 65 432 10 +0x07 DMTEMP[15:8] TEMPH Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 |
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