HT80C51 User Manual
List of Figures
Handshake Solutions
© Philips Electronics N.V. 2005
Page 131 of 132
A2: List of Figures
[Figure 1]
HT80C51 Architecture (CPU centered) .............................................................................. 7
[Figure 2]
HT80C51 Achitecture.......................................................................................................... 8
[Figure 3]
HT80C51 Memory Map....................................................................................................... 9
[Figure 4]
Memory map of Internal Data ........................................................................................... 10
[Figure 5]
Lower 128 bytes of RAM, direct and indirect addressing ................................................. 11
[Figure 6]
SFR memory map............................................................................................................. 13
[Figure 7]
Interrupt Response Timing Diagram................................................................................. 24
[Figure 8]
Interrupt Sources From the Timers 0 and 1...................................................................... 28
[Figure 9]
Timer/Counter mode 0: 13bit counter ............................................................................... 29
[Figure 10]
Timer/counter Mode 2: 8bit auto-reload. ....................................................................... 30
[Figure 11]
Timer/counter 0 mode 3: Two 8bit counters.................................................................. 30
[Figure 12]
Block Diagram of Serial Interface in Mode 0 ................................................................. 37
[Figure 13]
Block Diagram of Serial Interface in Mode 1, 2, and 3.................................................. 39
[Figure 14]
Typical I
2C Bus Configuration........................................................................................ 48
[Figure 15]
Data Transfer on the I
2C Bus ........................................................................................ 48
[Figure 16]
I
2C Bus Serial Interface Block Diagram......................................................................... 50
[Figure 17]
Arbitration Procedure..................................................................................................... 51
[Figure 18]
Serial Clock Synchronization......................................................................................... 52
[Figure 19]
Serial Input/Output Configuration .................................................................................. 54
[Figure 20]
Shift-in and Shift-out Timing .......................................................................................... 55
[Figure 21]
Format and States in the Master Transmitter mode...................................................... 61
[Figure 22]
Format and States in the Master Receiver Mode.......................................................... 62
[Figure 23]
Format and States in the Slave Receiver mode............................................................ 63
[Figure 24]
Format and States of the Slave Transmitter mode........................................................ 64
[Figure 25]
Simultaneous Repeated START Conditions from 2 Masters ........................................ 71
[Figure 26]
Forced Access to a Busy I2C Bus................................................................................. 72
[Figure 27]
Recovering from a Bus Obstruction Caused by a Low Level on SDA .......................... 73
[Figure 28]
SPI block diagram ......................................................................................................... 77
[Figure 29]
Data Clock Timing Diagram........................................................................................... 78
[Figure 30]
SPI Single Master Single Slave Configuration .............................................................. 79
[Figure 31]
Functional Diagram of the T3 Watchdog Timer............................................................. 81
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