AD7190

Preliminary Technical Data

Rev.PrD 7/08 | Page 16

STATUS REGISTER

(RS2, RS1, RS0 = 0, 0, 0; Power-On/Reset = 0x80)

The status register is an 8-bit read-only register. To access the ADC status register, the user must write to the communications register,

select the next operation to be a read, and load Bit RS2, Bit RS1, and Bit RS0 with 0. Table 15 outlines the bit designations for the status

register. SR0 through SR7 indicate the bit locations, SR denoting the bits are in the status register. SR7 denotes the first bit of the data

stream. The number in brackets indicates the power-on/reset default status of that bit.

SR7

SR6

SR5

SR4

SR3

SR2

SR1

SR0

RDY(1)

ERR(0)

NOREF(0)

PARITY(0)

CHD3(0)

CHD2(0)

CHD1(0)

CHD0(0)

Table 15. Status Register Bit Designations

Bit Location

Bit Name

Description

SR7

RDY

Ready Bit for ADC. Cleared when data is written to the ADC data register. The RDY bit is set automatically

after the ADC data register has been read or a period of time before the data register is updated with a

new conversion result to indicate to the user not to read the conversion data. It is also set when the part is

placed in power-down mode, idle mode or when SYNC is taken low.

The end of a conversion is also indicated by the DOUT/RDY pin. This pin can be used as an alternative to

the status register for monitoring the ADC for conversion data.

SR6

ERR

ADC Error Bit. This bit is written to at the same time as the RDY bit. Set to indicate that the result written to

the ADC data register has been clamped to all 0s or all 1s. Error sources include overrange, underrange, or

the absence of a reference voltage. Cleared by a write operation to start a conversion.

SR5

NOREF

No External Reference Bit. Set to indicate that the selected reference (REFIN1 or REFIN2) is at a voltage that

is below a specified threshold. When set, conversion results are clamped to all ones. Cleared to indicate

that a valid reference is applied to the selected reference pins. The NOXREF bit is enabled by setting the

REF_DET bit in the configuration register to 1. The ERR bit is also set if the voltage applied to the selected

reference input is invalid.

SR4

PARITY

Parity Check of Data Register.

If the ENPAR bit is set, the PARITY bit is set if there is an odd number of 1s in the data register. It is cleared if

there is an even number of 1s in the data register. The DAT_STA bit should be set when the parity check is

used. When the DAT_STA bit is set, the contents of the status register are transmitted along with the data

for each data register read.

SR3 to SR0

CHD3 to

CHD0

These bits indicate which channel corresponds to the data register contents. They do not indicate which

channel is presently being converted but indicate which channel was selected when the conversion

contained in the data register was being generated.

MODE REGISTER

(RS2, RS1, RS0 = 0, 0, 1; Power-On/Reset = 0x080060)

The mode register is a 24-bit register from which data can be read or to which data can be written. This register is used to select the

operating mode, the update rate, and the clock source. Table 16 outlines the bit designations for the mode register. MR0 through MR23

indicate the bit locations, MR denoting the bits are in the mode register. MR23 denotes the first bit of the data stream. The number in

brackets indicates the power-on/reset default status of that bit. Any write to the mode register resets the modulator and filter and sets the

RDY bit.

MR23

MR22

MR21

MR20

MR19

MR18

MR17

MR16

MD2(0)

MD1(0)

MD0(0)

DAT_STA(0)

CLK1(1)

CLK0(0)

0

0

MR15

MR14

MR13

MR12

MR11

MR10

MR9

MR8

SINC3(0)

0

ENPAR(0)

0

SINGLE(0)

REJ60(0)

FS9(0)

FS8(0)

MR7

MR6

MR5

MR4

MR3

MR2

MR1

MR0

FS7(0)

FS6(1)

FS5(1)

FS4(0)

FS3(0)

FS2(0)

FS1(0)

FS0(0)

Table 16. Mode Register Bit Designations

Bit Location

Bit Name

Description

MR23 to MR21

MD2 to MD0

Mode Select Bits. These bits select the operational mode of the AD7190 (see Table 17).

MR20

DAT_STA

Transmit status register contents after each data register read.

When DAT_STA is set, the contents of the status register are transmitted along with each data register