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M3882 Datasheet(PDF) 49 Page - Renesas Technology Corp |
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M3882 Datasheet(HTML) 49 Page - Renesas Technology Corp |
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49 / 62 page  Rev.1.01 Nov 14, 2005 page 49 of 60 REJ03B0089-0101 3882 Group Fig. 45 State transitions of system clock CM7, CM6: Main clock division ratio selection bit b7 b6 0 0 : φ = f(XIN)/2 ( High-speed mode) 0 1 : φ = f(XIN)/8 (Middle-speed mode) 1 0 : Not available 1 1 : Not available Notes Reset CM6 “1” ←→“0” CPU mode register b7 b6 (CPUM : address 003B16) CM7=0 CM6=1 Middle-speed mode (f( φ)=1 MHz) CM7=0 CM6=0 High-speed mode (f( φ)=4 MHz) 1 : Switch the mode by the allows shown between the mode blocks. (Do not switch between the modes directly without an allow.) 2 : The all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mode is ended. 3 : Timer operates in the wait mode. 4 : When the stop mode is ended, a delay of approximately 1 ms occurs by connecting prescaler 12 and Timer 1 in middle/high-speed mode. 5 : The example assumes that 8 MHz is being applied to the XIN pin . φ indicates the internal clock. |
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