M3882 datasheet(18/62 Pages) RENESAS

18 / 62 page

Rev.1.01

Nov 14, 2005

page 18 of 60

REJ03B0089-0101

3882 Group

Fig. 13 Structure of port I/O related registers (1)

Port control register 1

Port control register 2

P00–P03 output structure selection bit

0: CMOS

1: N-channel open-drain

P04–P07 output structure selection bit

0: CMOS

1: N-channel open-drain

P10–P13 output structure selection bit

0: CMOS

1: N-channel open-drain

P14–P17 output structure selection bit

0: CMOS

1: N-channel open-drain

P30–P33 pull-up control bit

0: No pull-up

1: Pull-up

P34–P37 pull-up control bit

0: No pull-up

1: Pull-up

Not used (returns “0” when read)

P45 P-channel output disable bit

0: CMOS output (in output mode)

1: N-channel open drain output (in output mode)

P7 input level selection bit (P70-P75)

0: CMOS input level

1: TTL input level

P4 output structure selection bit (P42, P43, P44, P46)

0: CMOS

1: N-channel open-drain

P8 function selection bit

0: Port P8/Port P8 direction register

1: Port P4 input register/Port P7 input register

INT2, INT3, INT4 interrupt switch bit

0: INT20, INT30, INT40 interrupt

1: INT21, INT31, INT41 interrupt

Not used (returns “0” when read)

Oscillation stabilizing time set after STP instruction released bit

0: Automatic set “0116” to timer 1 and “FF16” to prescaler 12

1: No automatic set

Not used (returns “0” when read)

(PCTL1: address 002E16)

(PCTL2: address 002F16)

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