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3820 Datasheet(PDF) 63 Page - Renesas Technology Corp |
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3820 Datasheet(HTML) 63 Page - Renesas Technology Corp |
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63 / 67 page ![]() 62 3820 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS _____ tw(RESET) tc(XIN) twH(XIN) twL(XIN) tc(CNTR) twH(CNTR) twL(CNTR) twH(INT) twL(INT) tc(SCLK1) twH(SCLK1) twL(SCLK1) tsu(RXD–SCLK1) th(SCLK1–RXD) tc(SCLK2) twH(SCLK2) twL(SCLK2) tsu(SIN2–SCLK2) th(SCLK2–SIN2) Note: When f(XIN) = 8 MHz and bit 6 of address 001A16 is “1” (clock synchronous). Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0” (UART). Reset input “L” pulse width Main clock input cycle time (XIN input) Main clock input “H” pulse width Main clock input “L” pulse width CNTR0, CNTR1 input cycle time CNTR0, CNTR1 input “H” pulse width CNTR0, CNTR1 input “L” pulse width INT0 to INT3 input “H” pulse width INT0 to INT3 input “L” pulse width Serial I/O1 clock input cycle time (Note) Serial I/O1 clock input “H” pulse width (Note) Serial I/O1 clock input “L” pulse width (Note) Serial I/O1 input set up time Serial I/O1 input hold time Serial I/O2 clock input cycle time Serial I/O2 clock input “H” pulse width Serial I/O2 clock input “L” pulse width Serial I/O2 input set up time Serial I/O2 input hold time Symbol Parameter Limits Min. µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted.) TIMING REQUIREMENTS 1 (Low Power Source Voltage Version) 2 125 45 40 250 105 105 80 80 800 370 370 220 100 1000 400 400 200 200 Typ. Max. Reset input “L” pulse width Main clock iuput cycle time (XIN input) Main clock input “H” pulse width Main clock input “L” pulse width CNTR0, CNTR1 input cycle time CNTR0, CNTR1 input “H” pulse width CNTR0, CNTR1 input “L” pulse width INT0 to INT3 input “H” pulse width INT0 to INT3 input “L” pulse width Serial I/O1 clock input cycle time (Note) Serial I/O1 clock input “H” pulse width (Note) Serial I/O1 clock input “L” pulse width (Note) Serial I/O1 input set up time Serial I/O1 input hold time Serial I/O2 clock input cycle time Serial I/O2 clock input “H” pulse width Serial I/O2 clock input “L” pulse width Serial I/O2 input set up time Serial I/O2 input hold time _____ tw(RESET) tc(XIN) twH(XIN) twL(XIN) tc(CNTR) twH(CNTR) twL(CNTR) twH(INT) twL(INT) tc(SCLK1) twH(SCLK1) twL(SCLK1) tsu(RXD–SCLK1) th(SCLK1–RXD) tc(SCLK2) twH(SCLK2) twL(SCLK2) tsu(SIN2–SCLK2) th(SCLK2–SIN2) Symbol Parameter Limits Min. µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit (VCC = 2.5 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted.) 2 125 45 40 900/ (VCC–0.4) 450/ (VCC–0.4)–20 450/ (VCC–0.4)–20 230 230 2000 950 950 400 200 2000 950 950 400 300 Typ. Max. Note: When f(XIN) = 2 MHz and bit 6 of address 001A16 is “1” (clock synchronous). Divide this value by four when f(XIN) = 2 MHz and bit 6 of address 001A16 is “0” (UART). TIMING REQUIREMENTS 2 (Low Power Source Voltage Version) |
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