| Electronic Components Datasheet Search |
|
3820 Datasheet(PDF) 64 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
3820 Datasheet(HTML) 64 Page - Renesas Technology Corp |
|
64 / 67 page ![]() 63 3820 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Measurement output pin 100pF CMOS output Note: When bit 4 of the UART control register (address 001B 16) is “1”. (N-channel open-drain output mode) Measurement output pin 100pF N-channel open-drain output (Note) 1k Ω Serial I/O1 clock output “H” pulse width Serial I/O1 clock output “L” pulse width Serial I/O1 output delay time (Note 1) Serial I/O1 output valid time (Note 1) Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output “H” pulse width Serial I/O2 clock output “L” pulse width Serial I/O2 output delay time Serial I/O2 output valid time Serial I/O2 clock output falling time CMOS output rising time (Note 2) CMOS output falling time (Note 2) 140 30 30 0.2!tC(SCLK2) 40 30 30 Symbol Parameter Limits Min. ns ns ns ns ns ns ns ns ns ns ns ns ns Unit (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted.) tc(SCLK1)/2–30 tc(SCLK1)/2–30 –30 tc(SCLK2)/2–160 tc(SCLK2)/2–160 0 10 10 Typ. Max. twH(SCLK1) twL(SCLK1) td(SCLK1–TXD) tv(SCLK1–TXD) tr(SCLK1) tf(SCLK1) twH(SCLK2) twL(SCLK2) td(SCLK2–SOUT2) tv(SCLK2–SOUT2) tf(SCLK2) tr(CMOS) tf(CMOS) Notes 1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. 2: XOUT and XCOUT pins are excluded. SWITCHING CHARACTERISTICS 1 (Low Power Source Voltage Version) Serial I/O1 clock output “H” pulse width Serial I/O1 clock output “L” pulse width Serial I/O1 output delay time (Note 1) Serial I/O1 output valid time (Note 1) Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output “H” pulse width Serial I/O2 clock output “L” pulse width Serial I/O2 output delay time Serial I/O2 output valid time Serial I/O2 clock output falling time CMOS output rising time (Note 2) CMOS output falling time (Note 2) 350 50 50 0.2!tC(SCLK2) 50 50 50 Symbol Parameter Limits Min. ns ns ns ns ns ns ns ns ns ns ns ns ns Unit (VCC = 2.2 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted.) tc(SCLK1)/2–50 tc(SCLK1)/2–50 –30 tc(SCLK2)/2–240 tc(SCLK2)/2–240 0 20 20 Max. twH(SCLK1) twL(SCLK1) td(SCLK1–TXD) tv(SCLK1–TXD) tr(SCLK1) tf(SCLK1) twH(SCLK2) twL(SCLK2) td(SCLK2–SOUT2) tv(SCLK2–SOUT2) tf(SCLK2) tr(CMOS) tf(CMOS) Notes 1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. 2: XOUT and XCOUT pins are excluded. SWITCHING CHARACTERISTICS 2 (Low Power Source Voltage Version) Typ. Fig.41 Circuit for measuring output switching characteristics |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |