4508 datasheet(46/142 Pages) RENESAS

46 / 142 page

Rev.1.02

2006.12.22

page 46 of 140

REJ03B0148-0102

4508 Group

M0–M7: Contents of master serial interface register

S0–S7: Contents of slave serial interface register

Rising of SCK: Serial input

Falling of SCK: Serial output

SIN

SOUT

Master

Slave

SCK

SST instruction

SOUT

SIN

S7’

SST instruction

SRDY signal

S7’

M7’

Fig. 39 Timing of serial interface data transfer

Table 16 Processing sequence of data transfer from master to slave

1-byte data is serially transferred on this process. Subsequently, data

can be transferred continuously by repeating the process from *.

When an external clock is selected as a synchronous clock, control

the clock externally because serial transfer is performed as long as

clock is externally input. (Unlike an internal clock, an external clock

is not stopped when serial transfer is completed.) However, the

Master (transmission)

[Initial setting]

• Setting the serial interface control register J1 and inter-

rupt control register V2 shown in Figure 38.

TJ1A and TV2A instructions

• Setting the port received the reception enable signal

(SRDY) to the input mode.

(Port D3 is used in this example)

SD instruction

* [Transmission enable state]

• Storing transmission data to serial interface register SI.

TSIAB instruction

[Transmission]

•Check port D3 is “L” level.

SZD instruction

•Serial transfer starts.

SST instruction

•Check transmission completes.

SNZSI instruction

•Wait (timing when continuously transferring)

Slave (reception)

[Initial setting]

• Setting serial interface control register J1, and interrupt control register V2

shown in Figure 38.

TJ1A and TV2A instructions

• Setting the port transmitted the reception enable signal (SRDY) and output-

ting “H” level.

(Port D3 is used in this example)

SD instruction

*[Reception enable state]

• The SIOF flag is cleared to “0.”

SST instruction

• “L” level (reception possible) is output from port D3.

RD instruction

[Reception]

• Check reception completes.

SNZSI instruction

• “H” level is output from port D3.

SD instruction

[Data processing]

SIOF flag is set to “1” when the clock is counted 8 times after ex-

ecuting the SST instruction. Be sure to set the initial level of the

external clock to “H.”

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