4508 datasheet(21/142 Pages) RENESAS

21 / 142 page

4508 Group

Rev.1.02

2006.12.22

page 21 of 140

REJ03B0148-0102

(6) Interrupt control registers

• Interrupt control register V1

Interrupt enable bits of external 0, timer 1 and timer 2 are as-

signed to register V1. Set the contents of this register through

used to transfer the contents of register V1 to register A.

• Interrupt control register V2

The A/D interrupt enable bit and serial interface interrupt enable bit

are assigned to register V2. Set the contents of this register

through register A with the TV2A instruction. The TAV2 instruction

can be used to transfer the contents of register V2 to register A.

Table 6 Interrupt control registers

Note: “R” represents read enabled, and “W” represents write enabled.

(7) Interrupt sequence

Interrupts only occur when the respective INTE flag, interrupt enable

bits (V10, V12, V13, V22, V23), and interrupt request flag are “1.” The

interrupt actually occurs 2 to 3 machine cycles after the cycle in

which all three conditions are satisfied. The interrupt occurs after 3

machine cycles only when the three interrupt conditions are satisfied

on execution of other than one-cycle instructions (Refer to Figure

16).

Interrupt disabled (SNZSI instruction is valid)

Interrupt enabled (SNZSI instruction is invalid)

Interrupt disabled (SNZAD instruction is valid)

Interrupt enabled (SNZAD instruction is invalid)

This bit has no function, but read/write is enabled.

R/W

TAV2/TV2A

V13

V12

V11

V10

V23

V22

V21

V20

Serial interface interrupt enable bit

A/D interrupt enable bit

Not used

Interrupt control register V2

at RAM back-up : 00002

at reset : 00002

Interrupt control register V1

Timer 2 interrupt enable bit

Timer 1 interrupt enable bit

Not used

External 0 interrupt enable bit

Interrupt disabled (SNZT2 instruction is valid)

Interrupt enabled (SNZT2 instruction is invalid)

Interrupt disabled (SNZT1 instruction is valid)

Interrupt enabled (SNZT1 instruction is invalid)

This bit has no function, but read/write is enabled.

Interrupt disabled (SNZ0 instruction is valid)

Interrupt enabled (SNZ0 instruction is invalid)

at RAM back-up : 00002

at reset : 00002

R/W

TAV1/TV1A

at RAM back-up : 00002

at reset : 00002

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