4553 datasheet(23/145 Pages) RENESAS

23 / 145 page

Rev.3.02

Dec 22, 2006

page 23 of 142

REJ03B0024-0302

4553 Group

(6) Interrupt control registers

• Interrupt control register V1

Interrupt enable bits of external 0, timer 1 and timer 2 are as-

signed to register V1. Set the contents of this register through

used to transfer the contents of register V1 to register A.

Table 6 Interrupt control registers

Note: “R” represents read enabled, and “W” represents write enabled.

• Interrupt control register V2

The timer 3 interrupt enable bit is assigned to register V2. Set the

contents of this register through register A with the TV2A instruc-

tion. The TAV2 instruction can be used to transfer the contents of

This bit has no function, but read/write is enabled.

Interrupt disabled (SNZT3 instruction is valid)

Interrupt enabled (SNZT3 instruction is invalid)

V13

V12

V11

V10

V23

V22

V21

V20

Not used

Timer 3 interrupt enable bit

Interrupt control register V2

at power down : 00002

at reset : 00002

Interrupt control register V1

Timer 2 interrupt enable bit

Timer 1 interrupt enable bit

Not used

External 0 interrupt enable bit

Interrupt disabled (SNZT2 instruction is valid)

Interrupt enabled (SNZT2 instruction is invalid)

Interrupt disabled (SNZT1 instruction is valid)

Interrupt enabled (SNZT1 instruction is invalid)

This bit has no function, but read/write is enabled.

Interrupt disabled (SNZ0 instruction is valid)

Interrupt enabled (SNZ0 instruction is invalid)

at power down : 00002

at reset : 00002

R/W

TAV1/TV1A

R/W

TAV2/TV2A

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