4570 datasheet(14/69 Pages) RENESAS

14 / 69 page

MITSUBISHI MICROCOMPUTERS

4570 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

INTERRUPT FUNCTION

The interrupt type is a vectored interrupt branching to an individual

address (interrupt address) according to each interrupt source.

An interrupt occurs when the following 3 conditions are satisfied.

• Interrupt enable flag (INTE) = “1” (Interrupt enabled)

• Interrupt enable bit = “1” (Interrupt request occurrence enabled)

• An interrupt activated condition is satisfied

(request flag = “1”)

Table 3 shows interrupt sources. (Refer to each interrupt request

flag for details of activated conditions.)

(1) Interrupt enable flag (INTE)

The interrupt enable flag (INTE) controls whether the every

interrupt enable/disable. Interrupts are enabled when INTE

flag is set to “1” with the EI instruction and disabled when

INTE flag is cleared to “0” with the DI instruction. When any

interrupt occurs, the INTE flag is automatically cleared to “0,”

so that other interrupts are disabled until the EI instruction is

executed.

(2) Interrupt enable bits (V10–V13, V20–V23)

Use an interrupt enable bit of interrupt control registers V1

and V2 to select the corresponding interrupt request or skip

instruction.

Table 4 shows the interrupt request flag, interrupt enable bit

and skip instruction.

Table 5 shows the interrupt enable bit function.

(3) Interrupt request flag

When the activated condition for each interrupt is satisfied,

the corresponding interrupt request flag is set to “1.” Each

interrupt request flag is cleared to “0” when either;

• an interrupt occurs, or

• the next instruction is skipped with a skip instruction.

Each interrupt request flag is set when the activated condition

is satisfied even if the interrupt is disabled by the INTE flag or

its interrupt enable bit. Once set, the interrupt request flag

retains set until a clear condition is satisfied.

Accordingly, an interrupt occurs when the interrupt disable

state is released while the interrupt request flag is set.

If more than one interrupt request flag is set when the interrupt

disable state is released, the interrupt priority level is as follows

shown in Table 3.

Table 3 Interrupt sources

Interrupt

address

Address 0

in page 1

Address 4

in page 1

Address 6

in page 1

Address 8

in page 1

Interrupt name

External 0 interrupt

Timer 1 interrupt

Timer 2 interrupt

Timer 3 interrupt

Activated condition

Level change of

INT pin

Timer 1 underflow

Timer 2 underflow

Timer 3 underflow

Priority

level

Table 4 Interrupt request flag, interrupt enable bit and skip

instruction

Interrupt name

External 0 interrupt

Timer 1 interrupt

Timer 2 interrupt

Timer 3 interrupt

Skip instruction

SNZ0

SNZT1

SNZT2

SNZT3

Request flag

EXF0

T1F

T2F

T3F

Enable bit

V10

V12

V13

V20

Table 5 Interrupt enable bit function

Skip instruction

Invalid

Valid

Interrupt enable bit

Occurrence of

interrupt request

Enabled

Disabled

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