SH7261 datasheet(353/1348 Pages) RENESAS

353 / 1348 page

Section 11 Direct Memory Access Controller (DMAC)

Rev. 2.00 Sep. 07, 2007 Page 321 of 1312

REJ09B0320-0200

Bit

Bit Name

Initial

Value

R/W

Description

10 to 8

DAMOD

[2:0]

Undefined R/W

Destination Address Direction Control

These bits are used to specify the direction of counting

for the source address.

000: Fixed

001: Incrementation

010: Decrementation

011: Rotation

100 to 111: Setting prohibited

7 to 4



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

SACT

Undefined R/W

DMA Active Signal Output for Source

This bit is used to control the output of the DMA-active

signal (DACT) for the source corresponding to the

requesting source setting in the DCTG bits.

When this bit is set to "0", output of the DACT signal is

disabled and the signal is fixed high unless the level

changes because of the DACT bit setting.

When this bit is set to "1", output of the DACT signal is

valid ("L") from the next cycle after the start of the

DMAC read cycle.

However, while output of the DACT signal is enabled

when the DMA request source selection bits (DCTG)

are set for software triggering, a valid DACT signal

cannot be output when the requesting source is an on-

chip peripheral circuit (DCTG), regardless of the

setting of the SACT bits.

0: Stops output of the DMA-active signal for the source

1: Selects output of the DMA-active signal for the

source during read access

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