SH7261 datasheet(355/1348 Pages) RENESAS

355 / 1348 page

Section 11 Direct Memory Access Controller (DMAC)

Rev. 2.00 Sep. 07, 2007 Page 323 of 1312

REJ09B0320-0200

Bit

Bit Name

Initial

Value

R/W

Description

1, 0

DTCM[1:0]

Undefined R/W

DMA End Signal Output Control

These bits are used to control the output of the DMA

end signal (DTEND) when the DMA transfer end

condition is detected.

When the bits are set to "00", DTEND signals on

completion of DMA transfer are disabled and the

DTEND line is fixed high.

When these bits are set to "10", the DTEND signal

goes low (is active) in the cycle after the read cycle

immediately preceding completion of DMA transfer.

When these bits are set to "10", the DTEND signal is

active in the cycle after the write cycle immediately

preceding completion of DMA transfer.

When these bits are set to "11", the DTEND signal is

active for the period of one clock cycle at the same

time as the DMA transfer end interrupt (for details, see

figure 11.9.)

However, while output of the DTEND signal is enabled

when the DMA request source selection bits (DCTG)

are set for software triggering, a valid DTEND signal

cannot be output when the requesting source is an on-

chip peripheral circuit (DCTG), regardless of the

setting of the DTEND bits.

00: Stops output of the DTEND signal

01: The DTEND signal is output on the last read cycle

10: The DTEND signal is output on the last write cycle

11: The DTEND signal is output after DMA has been

completed

Note:

Only write to this register when the corresponding channel is not engaged in single operand

transfer (the corresponding DASTS bit in the DMA arbitration status register (DMASTS) is

"0") and DMA transfer is disabled (DMST in the DMA activation control register (DMSCNT)

or DEN in DMA control register B for the channel (DMCNTBn) is set to "0"). Operation is not

guaranteed if this register is written to when both conditions are not satisfied.

When SACT and DACT are set to 1, output of a low DACT signal from the cycle following a

DMAC read or write cycle is enabled.

Table 11.3 shows the DMA source/destination address registers. For details on the rotation address

"indexing" mode, see section 11.11, Rotate Function. Note that when performing pipelined

transfer to or from external devices and modules that support burst access, make sure to set the

direction bits to select address incrementation ("001") or rotation ("011").

SH7261 Datasheet(PDF) 355 Page - Renesas Technology Corp

SH7261 Datasheet(HTML) 355 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL