SH7261 datasheet(357/1348 Pages) RENESAS

357 / 1348 page

Section 11 Direct Memory Access Controller (DMAC)

Rev. 2.00 Sep. 07, 2007 Page 325 of 1312

REJ09B0320-0200

Bit

Bit Name

Initial

Value

R/W

Description

29, 28

MDSEL

[1:0]

R/W

DMA Transfer Mode Selection

These bits are used to specify the DMA transfer mode.

Setting these bits to "00" selects cycle-stealing transfer

mode.

Setting these bits to "01" selects pipelined transfer

mode.

Do not set these bits to "10" or "11". Operation is not

guaranteed if these settings are made. For details, see

section 11.4.1, DMA Transfer Mode.

00: Cycle-stealing transfer

01: Pipelined transfer

10: Setting prohibited

11: Setting prohibited

Note:

Pipelined transfer through a single BIU is not

possible. For details on the BIU, see section

11.1, Features.

27, 26



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

25, 24

DSEL[1:0]

R/W

DMA Transfer Condition Selection

These bits are used to specify the conditions of DMA

transfer.

Setting these bits to "00" selects single operand

transfer.

Setting these bits to "01" selects sequential operand

transfer.

Setting these bits to "11" selects non-stop transfer. For

details, see section 11.4.2, DMA Transfer Condition.

Do not set these bits to "10". Operation is not

guaranteed if this setting is made.

00: Unit operand transfer

01: Sequential operand transfer

10: Setting prohibited

11: Non-stop transfer

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