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SH7261 Datasheet(PDF) 360 Page - Renesas Technology Corp |
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SH7261 Datasheet(HTML) 360 Page - Renesas Technology Corp |
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360 / 1348 page ![]() Section 11 Direct Memory Access Controller (DMAC) Rev. 2.00 Sep. 07, 2007 Page 328 of 1312 REJ09B0320-0200 Bit Bit Name Initial Value R/W Description 5 to 0 DCTG[5:0] 000000 R/W DMA Request Source Selection These bits specify the source of DMA requests. When selecting IIC3, SCIF, RCAN-ET, MTU2, or ADC as the source, set the DMA transfer request enable bits in DREQER0 to DREQER3 of the interrupt controller. For the settings of DREQER0–3, see section 6, Interrupt Controller (INTC). 000000: Software trigger 000001: DREQ0 pin 000010: DREQ1 pin 000011: DREQ2 pin 000100: DREQ3 pin 000101: IIC3 0ch RX 000110: IIC3 0ch TX 000111: IIC3 1ch RX 001000: IIC3 1ch TX 001001: IIC3 2ch RX 001010: IIC3 2ch TX 001011: SCIF 0ch RX 001100: SCIF 0ch TX 001101: SCIF 1ch RX 001110: SCIF 1ch TX 001111: SCIF 2ch RX 010000: SCIF 2ch TX 010001: SCIF 3ch RX 010010: SCIF 3ch TX 010011: SCIF 4ch RX 010100: SCIF 4ch TX 010101: SCIF 5ch RX 010110: SCIF 5ch TX 010111: SCIF 6ch RX |
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