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SH7261 Datasheet(PDF) 358 Page - Renesas Technology Corp |
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SH7261 Datasheet(HTML) 358 Page - Renesas Technology Corp |
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358 / 1348 page ![]() Section 11 Direct Memory Access Controller (DMAC) Rev. 2.00 Sep. 07, 2007 Page 326 of 1312 REJ09B0320-0200 Bit Bit Name Initial Value R/W Description 23 to 18 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 17, 16 STRG[1:0] 00 R/W Input Sense Mode Selection These bits specify input sense modes for DMA request signals input to the DMAC. The requesting source is that selected from among the possible sources by the DMA request source selection bits (DCTG). Select rising edge sense by setting these bits to "00" if the software trigger (DCTG = "000000") and pins DREQ0 to DREQ3 are selected as the source for DMA requests. Select falling edge sense by setting the bits to "10" when operation is with IIC3, SCIF, SSI, RCAN- ET, MTU2, ADC, or ROM-DEC (DCTG = "000101" to "100101"). Table 11.4 shows the relationships between DMA request sources and the possible input sense modes. 00: Rising edge 01: High level 10: Falling edge 11: Low level 15 to 11 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 10 BRLOD 0 R/W DMA Byte Count Reload Function Enable This bit specifies whether to reload the byte counter or not when the DMA transfer end condition is detected. When this bit is cleared to "0", no reload is executed. When this bit is set to "1" and the DMA transfer end condition is detected, the DMA current byte counter register (DMCBCTn) is reloaded with the value in the DMA reload byte count register (DMRBCTn). 0: Byte count reload function disabled 1: Byte count reload function enabled |
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