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SH7261 Datasheet(PDF) 362 Page - Renesas Technology Corp |
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SH7261 Datasheet(HTML) 362 Page - Renesas Technology Corp |
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362 / 1348 page  Section 11 Direct Memory Access Controller (DMAC) Rev. 2.00 Sep. 07, 2007 Page 330 of 1312 REJ09B0320-0200 Table 11.4 Relationships between DMA Request Sources and Input Sense Mode STRG Bit Settings DMA Request Source 00: Rising Edge Sense 01: High Level Sense 10: Falling Edge Sense 11: Low Level Sense DCTG Bit Setting Software trigger √ × × × 000000 DREQ0 pin √ √ √ √ 000001 DREQ1 pin √ √ √ √ 000010 DREQ2 pin √ √ √ √ 000011 DREQ3 pin √ √ √ √ 000100 IIC3 0ch RX × × √ × 000101 IIC3 0ch TX × × √ × 000110 IIC3 1ch RX × × √ × 000111 IIC3 1ch TX × × √ × 001000 IIC3 2ch RX × × √ × 001001 IIC3 2ch TX × × √ × 001010 SCIF 0ch RX × × √ × 001011 SCIF 0ch TX × × √ × 001100 SCIF 1ch RX × × √ × 001101 SCIF 1ch TX × × √ × 001110 SCIF 2ch RX × × √ × 001111 SCIF 2ch TX × × √ × 010000 SCIF 3ch RX × × √ × 010001 SCIF 3ch TX × × √ × 010010 SCIF 4ch RX × × √ × 010011 SCIF 4ch TX × × √ × 010100 SCIF 5ch RX × × √ × 010101 SCIF 5ch TX × × √ × 010110 SCIF 6ch RX × × √ × 010111 SCIF 6ch TX × × √ × 011000 SCIF 7ch RX × × √ × 011001 SCIF 7ch TX × × √ × 011010 |
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