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SH7261 Datasheet(PDF) 366 Page - Renesas Technology Corp |
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SH7261 Datasheet(HTML) 366 Page - Renesas Technology Corp |
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366 / 1348 page  Section 11 Direct Memory Access Controller (DMAC) Rev. 2.00 Sep. 07, 2007 Page 334 of 1312 REJ09B0320-0200 Bit Bit Name Initial Value R/W Description 16 DREQ 0 R/W (b) When a source other than the software trigger is selected (DCTG = "000000") by the DMA request source selection bits (DCTG) and a level sense has been selected • Condition for setting to "1" This bit is set to "1" when the DMA request input level matches that specified in the input sense selection bits (STRG), i.e. when a DMA request exists. • Condition for clearing to "0" This bit is cleared to "0" when the level specified by the input sense selection bits (STRG) and the level on the DMA request input do not match, i.e. when there is no DMA request. The DMA request is not retained if it disappears before being accepted; that is, the DMA request bit (DREQ) is cleared to "0". To use the DREQ bit with a level sense, continue the DMA request level until the request has been accepted. Note: When a requesting source other than the software trigger is selected, do not write "1" to the DMA request bit (DREQ). If "1" is written to this bit, operation is not guaranteed. |
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