SH7261 datasheet(367/1348 Pages) RENESAS

367 / 1348 page

Section 11 Direct Memory Access Controller (DMAC)

Rev. 2.00 Sep. 07, 2007 Page 335 of 1312

REJ09B0320-0200

Bit

Bit Name

Initial

Value

R/W

Description

DREQ

R/W

selected (DCTG = "000000") by the DMA request

source selection bits (DCTG) and an edge sense

has been selected

• Condition for setting to "1"

The DREQ bit is set to "1" when the edge specified

by the input sense selection bits (STRG) is

encountered, i.e. when a DMA request exists.

Once this bit has been set to "1", regardless of the

subsequent state of the DMA request signal, the

DMA request bit (DREQ) remains set until a

condition for clearing to "0" has been satisfied.

• Condition for clearing to "0"

This bit is cleared to "0" by either of the events

listed below.

 Software writing a "0" to this bit

 The start of operand transfer corresponding to

the bit

Notes: 1. In a case where a source other than

software triggering is selected, do not write

"1" to the DMA request bit (DREQ). If "1" is

written to this bit, operation is not

guaranteed.

2. After setting the DMA request source

selection bits (DCTG) and the input sense

mode selection bits (STRG) in DMA control

DMA request bit (DREQ) for the channel to

"0" and enable DMA transfer (DMST

= "1"

and DEN

= "1").

0: No DMA request

1: DMA requested

15 to 9



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

SH7261 Datasheet(PDF) 367 Page - Renesas Technology Corp

SH7261 Datasheet(HTML) 367 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL