SH7261 datasheet(371/1348 Pages) RENESAS

371 / 1348 page

Section 11 Direct Memory Access Controller (DMAC)

Rev. 2.00 Sep. 07, 2007 Page 339 of 1312

REJ09B0320-0200

11.3.11

DMA Interrupt Control Register (DMICNT)

DMICNT controls DMA interrupts for the respective channels.

Bit:

Initial value:

R/W:

9876543210

Bit:

Initial value:

R/W:

0000000000000000

R/W

RRRRRRRR

0000000000000000

RRRRRRRRRRRRRRRR

DINTM

—

—————————

Bit

Bit Name

Initial

Value

R/W

Description

31 to 24 DINTM

All 0

R/W

DMA Interrupt Control

These bits are used to control whether DMA transfer

end interrupts for the respective channels should be

generated for the interrupt controller.

When a bit is cleared to "0", interrupt requests for the

corresponding channel are not generated.

When these bits are set to "1", DMA transfer end

interrupts for the corresponding channel are generated

for the interrupt controller.

For details, see section 11.5.2, DMA Interrupt

Requests.

0: Interrupt disabled

1: Interrupt enabled

23 to 0



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

Note:

Bits 31 to 24 correspond to channels 0 to 7, respectively (31: channel 0, 30: channel

1. …24: channel 7).

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