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SH7261 Datasheet(PDF) 374 Page - Renesas Technology Corp |
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SH7261 Datasheet(HTML) 374 Page - Renesas Technology Corp |
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374 / 1348 page ![]() Section 11 Direct Memory Access Controller (DMAC) Rev. 2.00 Sep. 07, 2007 Page 342 of 1312 REJ09B0320-0200 11.3.14 DMA Transfer End Detection Register (DMEDET) DMEDET verifies the status of DMA transfer end detection for each channel. Writing 0 to the DEDET bit is invalid and 1 written to the bit is not retained. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit: Initial value: R/W: 15 14 13 12 11 10 9876543210 Bit: Initial value: R/W: 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W RRRRRRRR 0000000000000000 RRRRRRRRRRRRRRRR DEDET — — — — — — — — — — — — — — — ————————— |
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