SH7261 datasheet(378/1348 Pages) RENESAS

378 / 1348 page

Section 11 Direct Memory Access Controller (DMAC)

Rev. 2.00 Sep. 07, 2007 Page 346 of 1312

REJ09B0320-0200

11.4

Operation

11.4.1

DMA Transfer Mode

There are two DMA transfer modes

 cycle-stealing mode and pipelined mode. These modes are

selectable through the setting of the DMA transfer mode select bits (MDSEL) in DMA Control

Figure 11.2 gives examples of how bus mastership alternates between the DMAC and CPU in

various DMA transfer modes.

(1)

Cycle-stealing Transfer Mode

Cycle-stealing transfer mode is selected when the DMA transfer mode select bits are set to "00".

In cycle-stealing transfer mode, the DMAC leaves at least one cycle between the read and write

access cycles of each single data transfer. During this interval, the CPU can access the same target

BIU as the source or destination of its own operations. For details on the BIU, see section 11.1,

Features.

(2)

Pipelined Transfer Mode

Pipelined transfer mode is selected when the DMA transfer mode select bits are set to "01".

In pipelined transfer mode, DMAC activates the bus for read or write access, or both, on

consecutive cycles. Therefore, the CPU cannot access the target BIU as a source or destination

during single operand transfer.

Pipelined transfer through a single BIU is not possible either.

SH7261 Datasheet(PDF) 378 Page - Renesas Technology Corp