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SH7261 Datasheet(PDF) 379 Page - Renesas Technology Corp |
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SH7261 Datasheet(HTML) 379 Page - Renesas Technology Corp |
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379 / 1348 page ![]() Section 11 Direct Memory Access Controller (DMAC) Rev. 2.00 Sep. 07, 2007 Page 347 of 1312 REJ09B0320-0200 DMAC CPU DMAC CPU (4) (5) (6) (4) (5) (6) (3) (3) (3) (3) (3) (3) System clock Pipeline transfer mode (transfer between different BIU) Cycle steal transfer mode (transfer in the same BIU) System clock Read Read Read Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Write Write Write (3) CPU access to other than BIU on DMAC read/write side is possible (4) CPU access to other than BIU on DMAC read side is possible (5) CPU access to other than BIU on DMAC read/write side is possible (6) CPU access to other than BIU on DMAC write side is possible DMAC CPU (1) (1) (1) (1) (2) (2) (2) (2) System clock Single operand transfer Single operand transfer Single operand transfer Single operand transfer Single operand transfer Single operand transfer Read Read Read Read Write (1) CPU access to other than BIU on DMAC read side is possible (2) CPU access to other than BIU on DMAC write side is possible Cycle steal transfer mode (transfer between different BIU) Write Write Write Figure 11.2 Examples of the Alternation of Bus Mastership between the DMAC and CPU in Various DMA Transfer Modes |
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