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SH7261 Datasheet(PDF) 383 Page - Renesas Technology Corp |
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SH7261 Datasheet(HTML) 383 Page - Renesas Technology Corp |
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383 / 1348 page ![]() Section 11 Direct Memory Access Controller (DMAC) Rev. 2.00 Sep. 07, 2007 Page 351 of 1312 REJ09B0320-0200 Table 11.6 Relations between the mode and conditions of DMA transfer. DMA transfer mode condition Unit operand transfer DSEL = "00" Sequential operand transfer DSEL = "01" Non-stop transfer DSEL = "11" Cycle-stealing transfer MDSEL = "00" OK (between any two BIUs) OK (between any two BIUs) OK (between any two BIUs) Transfer mode Pipelined transfer MDSEL = "01" OK (between any two BIUs) OK (between any two BIUs) Mainly OK* (between any two BIUs other than BIU_E) Note: * The restriction means that non-stop transfer to the external SDRAM in pipelined transfer mode cannot be set up. |
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