SH7261 datasheet(384/1348 Pages) RENESAS

384 / 1348 page

Section 11 Direct Memory Access Controller (DMAC)

Rev. 2.00 Sep. 07, 2007 Page 352 of 1312

REJ09B0320-0200

11.4.3

DMA Activation

(1)

Initial Settings of the DMAC

Initial settings must be made in each of the relevant registers before the DMA transfer enable bit is

set (DEN

= "1"). These settings cannot be changed once transfer has started.

An example of DMAC registers that require initial settings is given below.

1. DMA mode register (DMMODn)

2. DMA control register A (DMCNTAn)

3. DMA control register B (DMCNTBn)

4. DMA current source address register (DMCSADRn)

5. DMA reload source address register (DMRSADRn)

 when the reload function is used

6. DMA current destination address register (DMCDADRn)

7. DMA reload destination address register (DMRDADRn)

 when the reload function is used

8. DMA current byte count register (DMCBCTn)

9. DMA reload byte count register (DMRBCTn)

 when the reload function is used

10. DMA interrupt control register (DMICNT)

 when an interrupt is used

11. DMA common interrupt control register (DMICNTA)

 when an interrupt is used

12. DMA transfer enable bit (DEN)

13. DMA activation control register (DMSCNT)

(2)

DMA Activation

DMA transfer for a channel is enabled by setting the DMA transfer enable bit (DEN) in DMA

control register B for the channel and the DMAC module activation bit (DMST) in the DMAC

activation register (DMSCNT) to "1".

When multiple DMA transfer requests are present, there is no complex mechanism for the

determination of channel priority. The DMA request that corresponds to the highest priority

channel is simply accepted and DMA transfer on that channel starts.

Whether a DMA request on a given channel is or is not present can be verified by testing the value

of the DMA request bit (DREQ) in DMA control register B (DMCNTBn) for that channel.

When a DMA request is accepted and DMA transfer starts, the DMA arbitration status bit

(DASTS) for the corresponding channel in the DMA arbitration status register (DMASTS) is set

to "1".

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