SH7261 datasheet(388/1348 Pages) RENESAS

388 / 1348 page

Section 11 Direct Memory Access Controller (DMAC)

Rev. 2.00 Sep. 07, 2007 Page 356 of 1312

REJ09B0320-0200

11.5.3

DMA End Signal Output

The form in which the DMA end signal (DTENDm) is output differs with the setting of the DMA

end signal output control bit (DTCM) in the DMA mode register (DMMODn) for the

corresponding channel.

• When DTCM is set to "00", output of the DTEND signal is not valid so the signal remains

fixed at the "H" level when and after the DMA transfer ends.

• When DTCM is set to "01", the DTEND signal becomes active (low) one cycle after the start

of the read cycle immediately before the end of DMA transfer (the read cycle for the last data

transfer).

• When DTCM is set to "10", the DTEND signal becomes active for one cycle after the write

cycle immediately before the end of DMA transfer (the write cycle for the last data transfer).

• When DTCM is set to "11", the DTEND signal becomes active for one clock cycle at the same

time as the DMA transfer end interrupt is generated.

Output of the DTEND signal is not valid in the case of DMA requests from external peripheral

circuits, so the signal remains fixed to "H" regardless of the setting of this bit.

Charts of the timing of DMA end signal output are given in figure 11.5.

Note:

The BSC is provided with a write buffer. Writing data to this buffer while writing to the

external devices stops bus access in the chip. Because of this, in DMA transfer to or from

external devices, the DTEND signal become disabled ("H") before the end of external bus

access. In this case the DTEND signal is not synchronized with the external bus access.

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